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The use of scattering parameters (S-parameters) to characterize high frequency interconnects has widely been used in the signal integrity field and is now being accepted into the disk drive arena as the preferred modeling tool for write and read path interconnects. The motivating factor for the shift from traditional lumped circuit models to S-parameter models has been the increase in data rates which exceed 1 GB/s. S-parameter models are convenient because they can be used directly in several high end spice circuit simulators as "black box" models. This paper will describe recent measurement techniques which make vector (VNA) network analyzer measurements possible for various interconnect structures up to 8.5 GHz. This paper will verify the results using time domain refiectometry (TDR) measurements of the same interconnect structures. Specific examples on signal losses, impedance, and coupling will be shown. Advances in achieving a broad range of differential impedances while maintaining high bandwidth will be demonstrated with idealized test structures. [ABSTRACT FROM AUTHOR]

High-rate low-density parity-check (LDPC) codes are the focus of intense research in magnetic recording because, when decoded by the iterative sum-product algorithm, they show decoding performance close to the Shannon capacity. However, cycles, especially short cycles, are harmful to LDPC codes. The paper describes the partition-and-shift LDPC (PS-LDPC) codes, a new class of regular, structured LDPC codes that can be designed with large girth and arbitrary large minimum distance. Large girth leads to more efficient iterative decoding and codes with better error-floor properties than random LDPC codes. PS-LDPC codes can be designed for any desired column weight and with flexible code rates. The paper details the girth and distance properties of the codes and their systematic construction and presents analytical and simulation performance results that show that, in the high signal-to-noise ratio region, PS-LDPC codes out- perform random codes, alleviating the error floor phenomenon. [ABSTRACT FROM AUTHOR]

The maximum transition run (MTR) and running digital sum (RDS) constraints have a wide variety of applications in magnetic recording systems. The property of an MTR constraint is to eliminate long runs of transitions so that certain common error events can be eliminated. The property of an RDS constraint is desirable for achieving high-density recording for recording channels exhibiting low frequency components, such as perpendicular recording channels. It is very common to implement more than one constraint in practice to achieve the desired effect in the recording channel. In this paper, the labeled graph representations of RDS and MTR [or the time-varying MTR (TMTR)] constraints are combined to obtain new classes of constraints: RDS-MTR and RDS-TMTR constraints. The capacity of a combined constraint is slightly lower than that of its constituent constraints. The spectra of RDS-MTR and RDS-TMTR constraints show the suppression of low frequency contents compared to the conventional MTR and TMTR constraints. A method for designing block codes is proposed to implement the properties of RDS, MTR (or TMTR), the run-length-limited (RLL) (0, k), and twin constraints. The cardinalities of block codes are maximized over various situations of codeword boundaries. The code design method- ology is demonstrated via a rate 100/108 RDS-TMTR block code based on a rate 20/21 RDS-TMTR mother code. [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel shockproof head gimbals assembly (HGA) structure incorporated with "a balanced-type head suspension" for 0.85-in hard disk drives (HDD5), and investigated its performance on external shock resistance during read/write operations. Experimental drop impact test results confirm that the 0.85-in drive equipped with the new suspension structure is durable over 2000 G (1.0 ms duration) of external shock, ensuring no head slider and/or disk surface damage. According to computer simulation and experimental results, potential shock resistance of more than 2000 G may also be possible with the head actuator itself, which points to its application in cellular phones. [ABSTRACT FROM AUTHOR]

Through an electrostatic discharge (ESD) damage case study of giant magnetoresistive (GMR) head in shunting process of head gimbal assemblies (HGA), this paper unveils that GMR heads would be damaged by a combination of field-induced voltage on HGA and surrounding trigger event. This investigation further demonstrates that the ESD protection technique, which derives from metal-to-metal contact to GMR terminals and thus focuses on eliminating metal-to-metal contact to GMR terminals, is not sufficient to prevent ESD. The electromagnetic interference caused by nearby trigger event needs to be noted also in the ESD control. [ABSTRACT FROM AUTHOR]

In a hard disk drive with a dual-stage actuator the standard rotary actuation of the voice coil motor (VCM) is combined with an additional micro- or milli-actuation to accomplish high-bandwidth and highly accurate track following. For extremely high density recording, the servo control algorithm designed for a specific dual-stage actuator needs to maintain high performance track following in lieu of external disturbances and uncertainties in the dynamic response induced by product manufacturing tolerances. Essential in the robust design of a servo control algorithm is to bound these uncertainties and design a robust track following servos accordingly. In this paper, we present an experiment based methodology to characterize and bound the uncertainties in the dynamic response of a dual-stage actuator in the form of an uncertainty model. Subsequently, the uncertainty model is used for the analysis and synthesis of a robust dual-stage servo controller that is able to optimize position error variance in the presence of uncertainty information. [ABSTRACT FROM AUTHOR]

A parity code and a distance enhancing constrained code are often concatenated with a Reed-Solomon code to form a coding system for magnetic recording. The tensor-product parity coding scheme helps to improve efficiency of the parity code while retaining the same level of performance. In this paper, we present two methods for combining a tensor-product parity code with a distance-enhancing constrained code. The first method incorporates a constrained code with unconstrained positions. The second method uses a new technique, which we call word-set partitioning, to achieve a higher code rate relative to the first method. We simulate the performance of several coding systems based upon the two combination methods on a perpendicular recording channel, and we compare their symbol error rates and sector error rates with those of a system that uses only a Reed-Solomon code. [ABSTRACT FROM AUTHOR]

Iterative codes such as low density parity check (LDPC) codes and turbo product codes (TPC) are of interest for data storage appli- çations. To apply these codes to digital recording systems, two possible schemes are considered in this paper. In the first scheme, a single LDPC code of column weight j > 2 is used to replace the Reed-Solomon (RS) code of the conventional channel. In the second scheme, an iterative code is used as the inner code and is concatenated with an outer RS code. Single parity check TPC code is considered for this scheme. We developed a high-throughput field programmable gate array (FPGA) platform to evaluate the error floor performance of LDPC codes and the error statistics of TPC codes in partial response (PR) channel with turbo equalization. High rate codes (rate 8/9 for LDPC code and rate 0.935 for TPC code) are evaluated for magnetic recoding application. The bit error rate (BER) performance of LDPC code down to 1010can be reached within 2 h using the FPGA platform. The TPC code error statistics are evaluated using about 1011 bits at different signal-to-noise (SNR) levels. For practical implementation complexity and power consumption, 2 channel iterations and 2 TPC decoder iterations are employed. The results show that the gain by applying TPC code under 2 channel iterations and 2 TPC decoder iterations is marginal. [ABSTRACT FROM AUTHOR]

We have three main goals in this paper. First, we will show the equivalences and relationships among some of the well-known classes of structured low density parity check (LDPC) codes. Second, we consider application of these codes to magnetic recording channel. We will make performance comparisons not only with bit-error-rate (BER) metric but also with sector failure rate (SFR) as the comparison dimension. Such a comparison is more meaningful from a system analysis perspective. Finally, we consider the case of these structured LDPC codes concatenated with conventional Reed-Solomon (RS) codes. We believe LDPC codes will not completely replace RS codes in the future storage devices. From this perspective, for LDPC codes to be contenders for future architectures, they will need to work in harmony with the outer RS codes. This implies that we have to take into account the redundancy introduced by the overall coding scheme, that is, RS code in concatenation with LDPC code, to reach meaningful comparisons from a system design perspective. [ABSTRACT FROM AUTHOR]

In this paper, we consider the problem of modeling the timing error process in magnetic recording systems. We propose a discrete- valued Markov model for the timing error process, and design two methods (data-aided and nondata-aided), based on the Baum-Welch algorithm, to extract the model parameters from the readback waveforms. The channel model we consider is an intersymbol interference (ISI) channel with additive Gaussian noise. The continuous-time readback signal at the output of the channel is sampled at baud-rate. Simulation results show that the estimated parameters are close to the actual values and the convergence is attained in a few iterations of the Baum-Welch algorithm. We also demonstrate the usefulness of the accurate model extraction by comparing a fine-tuned Markov timing recovery loop to the standard Mueller and Muller detector with a tuned second-order loop filter. [ABSTRACT FROM AUTHOR]

This paper reports on progress in perpendicular drive integration. In the first part, the performance of a series of perpendicular media with different coercivity (5-6 kOe), nucleation field, and soft-underlayer thickness (120/80 nm) is compared using two different head designs. Good overwrite and bit error rate performance is achieved for all head/media combinations. Higher coercivity leads to lower linear density but higher track density, resulting in approximately equal areal density capability. The thinner soft undelayer causes wider erase bands and therefore a loss of areal density. Wide-area track erasure measurements were performed on all media. The media with lower coercivity do not show any measurable amplitude loss, due to their larger absolute value of the nucleation field and the smaller write current needed to write on them. Two types of single-head, 7200 RPM desktop perpendicular drives (40 and 80 GB capacity) were built using 95 mm perpendicular media. They both achieve good bit error rate and off-track capability in all zones. The thermal decay for the 40 GB drive was measured and compared to a similar longitudinal drive. It was found that the thermal decay rate is much smaller in the case of the perpendicular drive in the range -6 °C to +80 °C. [ABSTRACT FROM AUTHOR]