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In this study, a 94 GHz PLL chip was designed using the integer-N PLL structure, and the results of a high-temperature test for the chip are discussed. The 94 GHz PLL was designed to exhibit a phase noise of −90 dBc/Hz or less at a 1 MHz offset frequency using a 0.13 μm SiGe BiCMOS process. In addition, a high-temperature test of the MIL-STD-331C standard was conducted on a manufactured 94 GHz SiGe PLL chip mounted on a test board. As a result of the test, the chip total current change before and after the high-temperature test was 4.7 %, and the phase noise changes of both 94 GHz VCO and PLL were 2.3 dB. These results confirm that, even after the high-temperature test, the flattening of the low-frequency noise was well maintained because the VCO noise was filtered by the PLL. [ABSTRACT FROM AUTHOR]

This paper verifies how the performance of the LC oscillator varies depending on the location of the negative gm-cell and proposes an optimal location of gm-cell in layout. Two LC-oscillators with the same core and inductor were designed, and only the location of the gm-cell was designed differently, and the performance of the two structures was compared. When the gm-cell is placed close to the main inductor, the phase noise is 2 dB better than when the gm-cell is placed far away from the inductor, and the power consumption is 15% less. Using the proposed design optimization process, the phase noise of -116.2 dBc/Hz @ 1 MHz in the 4.8 GHz is obtained. Then, the current consumption was 0.66-mA with 0.8-V supplay voltage. This performance is better than others works and this performance can support the BLE standard even if PVT changes. [ABSTRACT FROM AUTHOR]

In this study, a C~K band frequency synthesizer used in broadband electronic warfare equipment was designed, developed, and the meas- urement results were presented. The structure of the designed frequency synthesizer generates a signal up to 6 GHz using only direct digital synthesizer (DDS) without a mixer or multiplier. For signals above 6 GHz frequency, the structure uses a multiplier. In addition, a variable sampling frequency structure and a DDS circuit were designed to improve signal quality by reducing spurious signals, harmonic signals, and phase noise. The developed frequency synthesizer has different signal quality performance depending on the use of the multiplier, and the C∼G band has output power flatness ±1.7 dB, spurious signal less than −55 dBc, and phase noise less than −95 dBc/Hz (@1 kHz). The H~K band using multiplier has characteristics of output power flatness ±2.0 dB, spurious signal less than −35 dBc, and phase noise less than −80 dBc/Hz (@1 kHz). The results of this study confirmed the miniaturization of the signal generation module in the C∼K band. [ABSTRACT FROM AUTHOR]

This study proposes a frequency synthesizer with fast frequency modulation using a 28-nm CMOS process. The synthesizer used a two-point modulation technique that divides the frequency range into high- and low-pass regions to lock the frequency. In the high-pass region, continuous frequency modulation was achieved using a charge-digital-to-analog converter, while in the low-pass region, the synthesizer was set to the desired frequency using a divider and a delta-sigma modulator. The manufactured signal generator is capable of oscillating at frequencies between 14.1 GHz and 16.2 GHz, with a phase noise of −100.14 dBc/Hz at 1 MHz offset frequency. For chip signal generation, the generator had a chip time of 42.8 s and a bandwidth of 860 MHz. The chip area was 1,070×700 μm². [ABSTRACT FROM AUTHOR]

A static frequency-modulated continuous-wave (FMCW) radar imaging system uses different local oscillator (LO) and clock signals owing to the spatial separation of the transmitter and receiver, resulting in asynchronization problems of various factors that can deteriorate the quality of radar images. In this study, we defined signal models for bistatic FMCW asynchronization factors:1) the time difference between reference signals in the transmitter and receiver, 2) LO phase noise difference, 3) pulse repetition frequency mismatch, and 4) center frequency difference. We generated ISAR images of the point scatterer for each asynchronization factor to analyze the influence of asynchronization through the ISAR image in terms of quality parameters. [ABSTRACT FROM AUTHOR]

In this study, we propose a new method for measuring phase noise using an 8-channel digital oscilloscope, MXR608A, and the Labview software. The proposed phase noise measurement method obtains the time interval error (TIE) from a measured waveform using a digital oscilloscope; subsequently, it converts the TIE into phase noise. In the traditional phase-noise measurement method using TIE, the phase noise is obtained by cross-correlating two TIEs obtained from an identical signal. However, this method does not funda- mentally remove the effect of the ADC clock jitter when converting an analog signal into a digital signal. This study proposes a novel cross-correlation method that eliminates the ADC clock jitter and measures phase noise using the proposed cross-correlation. To verify the accuracy of the phase noise measured by the proposed method, a comparison is performed for the phase noise measured using the phase noise equipment E5052B. The two measured phase noises for a signal with an input power of 3 dBm per channel at a frequency of 1.4151 GHz exhibit the same offset frequency response in the range of 12 kHz to 10 MHz with an average difference of 0.2 dB. [ABSTRACT FROM AUTHOR]

FMICW radars detect and track targets using frequency information based on the distance and velocity of the target. Therefore, the phase noise of the received signal and the frequency resolution must be minimized to ensure detection and tracking accuracy of the radars. However, as the signal frequency increases, the phase noise degrades. Therefore, the design requirement of the phase noise is important for radar using high-frequency signals. In this study, the phase noise of the transmission signal (FTX), local oscillation signal (FLO1, FLO2), and reference signal (Fref) are analyzed for application to a W-band compact radar. Additionally, phase-noise require- ments are derived to increase the frequency resolution of the radar within a range that can be implemented in a W-band transceiver. [ABSTRACT FROM AUTHOR]

High-resolution compact radar in high-speed aerial vehicles can be exposed to vibration, and vibration can degrade the phase noise of crystal oscillators and other RF circuits. In this study, a laboratory experiment was conducted similar to the actual operating environment using a coherent frequency synthesizer, superheterodyne receiver realized by commercial RF circuits, an optical delay line with a maximum 20 km range delay, and a vibrator. After applying vibration to the frequency synthesizer, the phase noise was measured at each node of the receiver using a signal source analyzer. Consequently, it was confirmed that the effect of the phase noise suppression function depends on the range delay. The suppression function not only degrades the phase noise by frequency multiplication, but also degrades it by vibration. On the other hand, it has been shown theoretically and experimentally that the lower limit can be suppressed by the suppression function is determined by the higher level of the phase noise generated from the oscillator to the intermediate frequency signal or thermal noise. Finally, a transceiver architecture that has the advantage of suppressing phase noise is proposed for compact radar using high-resolution waveforms. [ABSTRACT FROM AUTHOR]

In this paper, we present the design, fabrication, and phase noise measurement of a 100 MHz voltage-controlled crystal oscillator (VCXO). The resonator used for the VCXO is a third-order overtone-mode crystal resonator with a resonance frequency of 100 MHz. The VCXO was fabricated on a 0.8 mm thickness FR4 two-layer substrate. The fabricated VCXO has an output power of approximately +8 dBm and a frequency of 99.992 MHz (approximately 8 kHz deviation from the center frequency of 100 MHz) at 0 V and 100.003 MHz (approximately 3 kHz deviation from 100 MHz) at 5 V. As a result, it has a frequency-tuning range of approximately 11 kHz. The measured phase noise showed −71.9 dBc/Hz at offset-frequency of 10 Hz and tuning voltage of 0 V. [ABSTRACT FROM AUTHOR]

This paper concerns a PLL design operating at 2.45 GHz and a method for checking frequency and phase errors over time. During the design process, the design method had a natural frequency (ωn) of 33,800 rad/s and a damping ratio (ζ) of 0.53 according to a generally known method of designing a Type-Ⅱ PLL. Owing to production, when the PLL of VCO(voltage controlled oscillator) was added, phase noise decreased by 22 dB and 58 dB at 10 kHz and 150 kHz offset, respectively. In the experimental stage of the characteristics, the result of calculating the interval between the peak points of the initial frequency error in the circuit designed using MATLAB program was 100 μs, and a similar result was obtained when the measurement was taken using an oscilloscope. It was assumed that the highest point of the output frequency was 2.5 GHz through the change of the tuning voltage measured using the oscilloscope, and it was verified by using mixer that a maximum output frequency was 2.504 GHz. Additionally, for the compensation of the phase error at the comparison frequency, we obtained values of 12.7° and 8.93° using an oscilloscope and a PSpice, respectively, after fixing the frequency. The error between the two measurements was 29.7 %, and it was determined to be due to approximation in the integration process and the fluctuation of the tuning voltage. [ABSTRACT FROM AUTHOR]

Unlike conventional frequency-locked loop(FLL) oscillators, in this paper, a novel FLL-frequency synthesizer(FLL-FS) is proposed using a resonator with a resonance frequency fL lower than the oscillation frequency. The proposed FLL-FS oscillates at nfL (n is an integer), and comprises a voltage-controlled oscillator(VCO), frequency divider, and frequency detector(FD). To verify the feasibility of the proposed FLL-FS structure, a prototype FLL-FS is presented. The selected resonator was a surface-mount ceramic resonator with a resonance frequency of 11.255 MHz. The FD consists of the selected resonator and an XOR-phase detector. The frequency divider is a fixed-frequency divider and has a division ratio of 128/129. The selected VCO has a frequency tuning range that includes a multiplied frequency of 11.255 MHz by 128/129. The fabricated frequency synthesizer demonstrated a successful FLL-FS operation, and the measured phase noise was −91 dBc/Hz at an offset frequency of 100 kHz. [ABSTRACT FROM AUTHOR]

This paper reports a fractional-N phase-locked-loop(PLL) frequency synthesizer that is implemented in a 0.35-μm standard CMOS process and generates a quadrature signal for an FRS terminal. The synthesizer consists of a voltage-controlled oscillator(VCO), a charge pump(CP), loop filter(LF), a phase frequency detector(PFD), and a frequency divider. The VCO has been designed with an LC resonant circuit to provide better phase noise and power characteristics, and the CP is designed to be able to adjust the pumping current according to the PFD output. The frequency divider has been designed by a 16-divider pre-scaler and fractional-N divider based on the third delta-sigma modulator(3rd DSM). The LF is a third-order RC filter. The measured results show that the proposed device has a dynamic frequency range of 460～510 MHz and -3.86 dBm radio-frequency output power. The phase noise of the output signal is -94.8 dBc/Hz, and the lock-in time is 300 μs. [ABSTRACT FROM AUTHOR]

A phase frequency detector(PFD) composed of logic circuits is widely used in a phase locked loop(PLL) due to the easy implementation for integrated circuits. A frequency locked loop(FLL) removes the reference oscillator in the PLL, and the resonator serves as a reference oscillator. A frequency detector(FD) is indispensable for the FLL configuration, and a FD, which is usually composed of a mixer is used to build an FLL. In this paper, instead of FD using mixer, a FD is constructed by using 1.175 GHz resonator composed of microstrip and PFD taking the versatility of PFD into consideration. Using the designed FD, FLL oscillating at a frequency of 1.175 GHz is composed. As a result of comparison with the FLL composed of FD using mixer, it was confirmed that the proposed FLL has better phase noise performance than FLL using mixer FD with FLL bandwidth. [ABSTRACT FROM AUTHOR]

In this paper, a phase locked loop structure with parallel dual loop which have a different bandwidth has been proposed. The bandwidths depending on transfer functions are obtained through dual loops. Two different bandwidths of each loop are used to suppress noise on the operating frequency range. The proposed phase locked loop has two different voltage controlled oscillator gains to control two different wide and narrow loop filters. Furthermore, it has the locking status indicator to achieve an accurate locking condition. The phase margin of 58.2° for wide loop and 49.4° for narrow loop is designed for stable operation and the phase margin of 45° is maintained during both loops work together. It has been designed with a 1.8V 0.18㎛ complementary metal oxide semiconductor (CMOS) process. The simulation results show that the proposed phase locked loop works stably and generates a target frequency. [ABSTRACT FROM AUTHOR]

As the integration of circuit components increases steadily, various EMS(Electromagnetic Susceptibility) problems have emerged from integrated circuits and electrical systems. The electromagnetic susceptibility of VCOs(Voltage Controlled Oscillator) is especially critical in RF systems. Therefore, in this paper, through the phase noise theory that models electrical oscillators as linear time variant systems, the EMS characteristics of representative VCO -ring VCO and LC VCO- with 1.2 GHz of reference oscillating frequency are analyzed under the existence of the electromagnetic noise coupled in power supply. An simulation algorithm is developed to extract impulse response function based on the phase noise theory. When there is no supply noise, the magnitude of the jitter of two oscillators were similar to around 2.1 ps, but in presence of supply noise, the jitter was significantly lower in LC VCOs than ring VCOs. [ABSTRACT FROM AUTHOR]

This paper proposes a high speed frequency synthesizer with dual phase-locked loop(PLL) structure to improve phase noise level and shape in a wideband receiver. To reduce phase noise and fractional spur, a output frequency of 1st PLL used as reference frequency of 2nd PLL is changed. The frequency synthesizer has been designed with 1 Hz frequency resolution using digital NCO in 6.5～8.5 GHz wide spectrum. The measured results of the fabricated frequency synthesizer show that the output power is about —3 dBm, the maximum lock-in time and phase noise are within 60 us and —95 dBc/Hz at 10 kHz offset, respectively. [ABSTRACT FROM AUTHOR]