UHF FRS 대역 CMOS PLL 주파수 합성기 설계.

This paper reports a fractional-N phase-locked-loop(PLL) frequency synthesizer that is implemented in a 0.35-μm standard CMOS process and generates a quadrature signal for an FRS terminal. The synthesizer consists of a voltage-controlled oscillator(VCO), a charge pump(CP), loop filter(LF), a phase frequency detector(PFD), and a frequency divider. The VCO has been designed with an LC resonant circuit to provide better phase noise and power characteristics, and the CP is designed to be able to adjust the pumping current according to the PFD output. The frequency divider has been designed by a 16-divider pre-scaler and fractional-N divider based on the third delta-sigma modulator(3rd DSM). The LF is a third-order RC filter. The measured results show that the proposed device has a dynamic frequency range of 460～510 MHz and -3.86 dBm radio-frequency output power. The phase noise of the output signal is -94.8 dBc/Hz, and the lock-in time is 300 μs. [ABSTRACT FROM AUTHOR]