171 results on '"Yamashina M"'
Search Results
2. A low-power W-CDMA demodulator using specially-designed micro-DSPs.
3. A 0.10 μm CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation VCO.
4. Reconfigurable computing: its concept and a practical embodiment using newly developed dynamically reconfigurable logic (DRL) LSI.
5. Spatial-temporal mapping of real applications on a Dynamically Reconfigurable Logic Engine (DRLE) LSI.
6. A 400 MHz, 300 mW, 8 kb, CMOS SRAM macro with a current sensing scheme.
7. Video signal processor (VSP) ULSIs for video data coding (in teleconferencing).
8. A study on mobile multi-media terminal construction for PHS.
9. Generalized Equation for the Force-Frequency Characteristics of Circular Quartz Plates with Three-Point Support and Its Application to Supporting of an SC-Cut Plate.
10. Interconnect Design Strategy for High-Speed Logic LSIs.
11. Realtime video signal processor module.
12. Video signal processor configuration by multiprocessor approach.
13. 100 MHz, 0.55 mm/sup 2/, 2 mW, 16-b stacked-CMOS multiplier-accumulator.
14. A 500-MHz, 0.4-/spl mu/m CMOS, 32-word by 32-bit 3-port register file.
15. Association of the TNF-{alpha}-C-857T polymorphism with resistance to the cholesterol-lowering effect of HMG-CoA reductase inhibitors in type 2 diabetic subjects.
16. A 2000-MOPS embedded RISC processor with a Rambus DRAM controller.
17. Inherited complete deficiency of 20-kilodalton homologous restriction factor (CD59) as a cause of...
18. Generalized Equation for the Force-Frequency Characteristics of Circular Quartz Plates.
19. A real-time video signal processor suitable for motion picture coding applications.
20. An 800-MOPS, 110-mW, 1.5-V, parallel DSP for mobile multimedia processing.
21. A 1.5-W single-chip MPEG-2 MP@ML video encoder with low power motion estimation and clocking.
22. A 0.25-/spl mu/m CMOS 0.9-V 100-MHz DSP core.
23. A GHz MOS adaptive pipeline technique using MOS current-mode logic.
24. A current direction sense technique for multiport SRAM's.
25. Capacitance coupling immune, transient sensitive accelerator for resistive interconnect signals of subquarter micron ULSI.
26. Design of 1.28-GB/s high bandwidth 2-Mb SRAM for integrated memory array processor applications.
27. A single-board video signal processor module employing newly developed LSI devices.
28. A variant of early gastric carcinoma. Histologic and histochemical studies of early signet ring cell carcinomas discovered beneath preserved surface epithelium.
29. Primary squamous cell carcinoma with its spindle cell variant in the endometrium. A case report and review of literature.
30. A 500 MHz, 32 bit, 0.4 /spl mu/m CMOS RISC processor.
31. A 3.84 GIPS integrated memory array processor with 64 processing elements and a 2-Mb SRAM.
32. A 300-MHz 16-b 0.5-/spl mu/m BiCMOS digital signal processor core LSI.
33. A 300-MHz 16-b BiCMOS video signal processor.
34. 250-MHz BiCMOS super-high-speed video signal processor (S-VSP) ULSI.
35. A 200-MHz 16-bit super high-speed signal processor (SSSP) LSI.
36. A microprogrammable real-time video signal processor (VSP) for motion compensation.
37. A microprogrammable real-time video signal processor (VSP) LSI.
38. On-chip multi-GHz clocking with transmission lines.
39. A 1 GHz portable digital delay-locked loop with infinite phase capture ranges.
40. Clock distribution networks with on-chip transmission lines.
41. An embedded DRAM-FPGA chip with instantaneous logic reconfiguration.
42. An automatic sorting system for glass bottles, cans, and plastic bottles.
43. Frequency Changes in Fifth-Overtone 5-MHz Circular Plano-Convex AT- And LT-Cut Plates Due to Radially Applied Three Forces.
44. A 500 MHz 32b 0.4 /spl mu/m CMOS RISC processor LSI.
45. A 3.84 GIPS integrated memory array processor LSI with 64 processing elements and 2 Mb SRAM.
46. Capacitance coupling immune, transient sensitive accelerator for resistive interconnection signals of sub-quarter micron ULSI.
47. A current direction sense technique for multi-port SRAMs.
48. A 1.5 W single-chip MPEG2 MP@ML encoder with low power motion estimation and clocking.
49. An autonomous reconfigurable cell array for fault-tolerant LSIs.
50. Elastic-Vt CMOS circuits for multiple on-chip power control.
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.