A 0.10 μm CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation VCO.

Authors :: Minami, K.
Fukaishi, M.
Mizuno, M.
Onishi, H.
Noda, K.
Imai, K.
Horiuchi, T.
Yamaguchi, H.
Sato, T.
Nakamura, K.
Yamashina, M.
Source :: Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169); 2001, p213-216, 4p
Publication Year :: 2001

Language :: English
ISBNs :: 9780780365919
Database :: Complementary Index
Journal :: Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)
Publication Type :: Conference
Accession number :: 81247629
Full Text :: https://doi.org/10.1109/CICC.2001.929758