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Detailed state-space modeling and analysis of a class of RF switched-capacitor power amplifiers achieving high efficiency, output power, and linearity are presented. Time-domain voltage and current waveforms are analytically obtained via the steady-state solution of the amplifier’s model equations. The output power of the fundamental and that of the harmonics, as well as the drain efficiency of the switched-capacitor power amplifier (SCPA) are derived. The state-space model is implemented in MATLAB and all theoretical results are compared to Cadence Spectre simulation of the SCPA and are found to be in good agreement. [ABSTRACT FROM AUTHOR]

The IEEE 802.11ad standard supports PHY rates up to 6.7 Gbps on four 2 GHz-wide channels from 57 to 64 GHz. A 60 GHz system offers higher throughput than existing 802.11ac solutions but has several challenges for high-volume production including: integration in the host platform, automated test, and high link loss due to blockage and polarization mismatch. This paper presents a 802.11ad radio chipset capable of SC and OFDM modulation using a 16TX-16RX beamforming RF front-end, complete with an antenna array that supports polarization diversity. To aid low-cost integration in PC platforms, a single coaxial cable interface is used between chips. The chipset is capable of maintaining a link of 4.6 Gbps (PHY rate) at 10 m. [ABSTRACT FROM AUTHOR]

This paper presents a direct conversion, multistandard TV tuner implemented on a 65 nm digital CMOS process occupying less than 7 mm². The tuner is compliant with several digital terrestrial, fixed and mobile TV standards, including DVB-T, DVB-H, T-DMB, and ISDB-T. It achieves a 3/3.2/3.5 dB noise figure at VHF, UHF, and L-band, respectively, while the measured sensitivity at UHF for the QPSK-½ DVB-T mode is -98 dBm at the PCB connector. The implemented RF front-ends support both single-ended and differential inputs. An integrated Σ-Δ fractional-N synthesizer operating from 1.2 to 1.8 GHz achieves less than 1° integrated phase error, thus enabling a maximum SNR in excess of 37 dB for VHF and UHF. Multistandard capability is also enabled by programmable channel-select filters. Power consumption is less than 140 mW in DVB-T mode for all three bands. [ABSTRACT FROM AUTHOR]

The drive for cost reduction has led to the use of CMOS technology in the implementation of highly integrated radios. This paper presents a single-chip 5-GHz fully integrated direct conversion transceiver for IEEE 802.11a WLAN systems, manufactured in 0.18-µm CMOS. The IC features an innovative system architecture which takes advantage of the computing resources of the digital companion chip in order to eliminate I/Q mismatch and achieve accurately matched baseband filters. The integrated voltage-controlled oscillator and synthesizer achieve an integrated phase noise of less than 0.8° rms. The receiver has an overall noise figure of 5.2 dB and achieves sensitivity of -75 dBm at 54-Mb/s operation, both referred to the IC input. The transmit error vector magnitude is -33 dB at -5-dBm output power from the integrated power-amplifier driver amplifier. The transceiver occupies an area of 18.5 mm². [ABSTRACT FROM AUTHOR]