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Thermomechanical analysis of monolithic microwave integrated circuit (MMIC) packaging is essential to guarantee the reliability of radio frequency/microwave applications. However, a method for fast and accurate analysis of MMIC packaging structures has not been developed. Here, a machine learning (ML)‐based solution for thermomechanical analysis of MMIC packaging is demonstrated. This ML‐based solution analyzes temperature and thermal stresses considering key design parameters, including material properties, geometric characteristics, and thermal boundary conditions. Finite element simulation with the Monte Carlo method is utilized to prepare a large dataset for supervised learning and validation of the ML solution, and a laser‐assisted thermal experiment is conducted to verify the accuracy of the simulation. After data preparation, regression tree ensemble and artificial neural network (ANN) learning models are investigated. The results show that the ANN model accurately predicts the outcomes with extremely low computing time by analyzing the high‐dimensional dataset. Finally, the developed ML solution is deployed as a web application format for facile approaches. It is believed that this study will provide a guideline for developing ML‐based solutions in chip packaging design technology. [ABSTRACT FROM AUTHOR]

The roll-to-roll (R2R) continuous patterning of silver nanowire-polyvinylpyrrolidone (Ag NW-PVP) composite transparent conductive film (cTCF) is demonstrated in this work by means of slot-die coating followed by selective calendering. The Ag NWs were synthesized by the polyol method, and adequately washed to leave an appropriate amount of PVP to act as a capping agent and dispersant. The as-coated Ag NW-PVP composite film had low electronic conductivity due to the lack of percolation path, which was greatly improved by the calendering process. Moreover, the dispersion of Ag NWs was analyzed with addition of PVP in terms of density and molecular weight. The excellent dispersion led to uniform distribution of Ag NWs in a cTCF. The continuous patterning was conducted using an embossed pattern roll to perform selective calendering. To evaluate the capability of the calendering process, various line widths and spacing patterns were investigated. The minimum pattern dimensions achievable were determined to be a line width of 0.1 mm and a line spacing of 1 mm. Finally, continuous patterning using selective calendering was applied to the fabrication of a flexible heater and a resistive touch sensing panel as flexible electronic devices to demonstrate its versatility. [ABSTRACT FROM AUTHOR]

We modeled flexible microelectronic systems, in which a thinned silicon die is flip-chip bonded to a flexible substrate, and analyzed the stress and strain distribution generated during twisting deformation. Because of the presence of the rigid silicon die, the strain distribution of the system model was significantly different from that of the substrate model. Unlike the substrate model, there is no significant difference in the von Mises strain according to the position in both the molding layer and the substrate in the system model. Therefore, the results of modeling or testing only flexible substrate cannot be directly applied to predict the behavior of flexible microelectronic systems. The copper bumps revealed stress above the ultimate strength as well as the yield strength. Therefore, the copper bump would be the most mechanically weak component in the operation of the face-down flexible microelectronic system during twisting. By replacing copper bumps with polymer bumps, the maximum stress in the bumps can be significantly reduced from 282 to 47 MPa, and the maximum mechanically safe twisting angle was also improved from approximately 40° to 80°. Therefore, in flexible electronic systems where twisting deformation is applied, polymer bumps are a better bonding method than the conventional copper bumps. [ABSTRACT FROM AUTHOR]

In this article, the condition diagnosis and form error prediction models for lens injection moulding process are developed based on a response surface method by using features extracted from in-process cavity pressure signals. In the lens injection moulding experiments, cavity pressure signals are captured by pressure sensors embedded in a lens mould, and form errors of manufactured lenses are measured afterwards. Then, three features such as filling point, maximum pressure and inflection point pressure are identified from the measured cavity pressure profile, and they are used to formulate the response surface functions for each injection moulding condition. In addition, the response surface functions for the lens form error with the input variables of the above-mentioned three features are also formulated. It is reported that the overall average accuracies for the lens injection moulding condition diagnosis and form error estimation are better than 97% and 80%, respectively, in the actual industrial site. [ABSTRACT FROM AUTHOR]

A new through-silicon via (TSV) build-up stacking method using oxide bonding is proposed and implemented in this work. The proposed method can be applied to the fabrication of a TSV stack chip. Thermal stress analysis was carried out to compare the structural reliability between conventional TSV and the proposed TSV model. The simulation results indicate that the proposed TSV model is more reliable than the conventional model with respect to stress in the stack chip. Experiments were conducted by oxide bonding of chips and the oxide bonding energy was acquired by a four point bending test. The obtained bonding energy sufficiently exceeds the energy criteria of 3D stacking. Thus, two oxide wafers with an 8 inch diameter were bonded by oxide bonding at the wafer level. The 0.6 μm thick oxide layers were located between bonded wafers and the top wafer was thinned down to fabricate blind via at the top of bonded wafer. The thickness of the top and bottom wafer is to 70 and 725 μm, respectively, after the top chemical mechanical polishing (CMP) process. Then blind vias were fabricated by deep reactive ion etching; the diameter and depth of the via is 20 μm and 150 μm, respectively. A through hole was formed by bottom CMP; total thickness of the oxide bonded wafer is 140 μm. The dielectric layer (SiO2), adhesion and diffusion barrier (TiN, Ti) and wetting layer (Cu) were deposited sequentially to improve the wettability of the via wall. Since the molten solder cannot be filled in the via if there is no wetting layer at the via wall. Finally, the vias were successfully filled with molten solder within 10 s. [ABSTRACT FROM AUTHOR]

An efficient edge-tracing technique at the wafer-level is proposed and implemented in this paper. The proposed method can be applied to the fabrication of a stacked chip. Experiments were conducted by stacking four test chips each 100-\mum-thick, and the configuration of the pad is based on a memory chip from an electronics company. The chips for stacking were fabricated by half-dicing the wafer and curing the adhesives in a trench. When the four chips were built up and metallized, the stacked chip was 430-\mum high, which is comparable to that of a through-silicon via. The daisy chain resistance of the interconnection was measured to be 5 \Omega, and further improvement is possible with modification. The interconnection quality of the stacked chip was examined through 3-D images obtained via computed tomography and X-ray imageries. The images proved the successful creation of the interconnections. The mechanical integrity of the stacked package meets the 85^\circC/85% relative humidity test, and the thermal stress analysis is implemented to investigate the reliability issues at the edge of the chip, and it is concluded that there are no critical reliability problems. [ABSTRACT FROM AUTHOR]

Although the groove and slot have been widely utilized for horn design to achieve high uniformity, their effects on uniformity have not been analyzed thoroughly. In this work, spool and bar horns for ultrasonic bonding are designed in a systematic way using the design of experiments (DOE) to achieve high amplitude uniformity of the horn. Three-dimensional modal analysis is conducted to predict the natural frequency, amplitude, and stress of the horns, and the DOE is employed to analyze the effects of the groove and slot on the amplitude uniformity. The design equations are formulated to determine the optimum dimensions of the groove and slot, and the uniformity is found to be influenced most significantly by the groove depth and slot width. Displacements of the spool and bar horns were measured using a laser Doppler vibrometer (LDV), and the predicted results are in good agreement with the experimental data. [ABSTRACT FROM AUTHOR]

Thin silicon wafers are usually used for many devices and electronic fabrication development. But handling thin wafers are not easy since thin wafers may lose the supporting strength and crack. Using adhesives is the one of the possible solutions for thin wafer handling, and how to synthesize adhesives materials and investigate debonding behaviors for temporary bonding and debonding are an important research. In this work, laser irradiation is considered for debonding temporary adhesives in a 3D multi-chip package process because of its very fast debonding time about few seconds and irradiation stability than thermal or chemical debonding. The thermal curable adhesives were fast cured on high temperature by the laser irradiation. The emphasis is the choice of the specific laser process parameters such as the out-focusing length, the line spacing, and the scan speed. The surface morphology with various sets of these parameters is examined by optical microscopy. Also, peel strength before/after the laser irradiation is investigated. Based on this study, suitable process parameters and conditions are proposed for clean surface of silicon wafers and lower peel strength for easy debonding. [ABSTRACT FROM AUTHOR]

Abstract: Multi-chip packages (MCP) refers to a packaging configuration, connected via wirebonds to a multilayer circuit board, and protected by either a molded encapsulant or a low-cost ceramic package. As it requires high processing temperature, the adhesives for MCP need to show proper adhesion and thermal stability at high temperature. This study employed semi-interpenetrated (semi-IPN) structured polymer networks using UV-curing with acrylate terminated dual-curable urethane epoxy adhesive, a dipentaerythritol hexacrylate (DPHA), using hydroxydimethyl acetophenone as photo-initiator. UV-curing and thermal stability focused on different photo-initiator contents were investigated using photo-DSC, FTIR-ATR spectroscopy, gel content and TGA. The results show that UV-curable acrylic formulations with different content of photo-initiator affects UV-curing and thermal stability. [Copyright &y& Elsevier]

The roll-to-roll (R2R) continuous patterning of silver nanowire-polyvinylpyrrolidone (Ag NW-PVP) composite transparent conductive film (cTCF) is demonstrated in this work by means of slot-die coating followed by selective calendering. The Ag NWs were synthesized by the polyol method, and adequately washed to leave an appropriate amount of PVP to act as a capping agent and dispersant. The as-coated Ag NW-PVP composite film had low electronic conductivity due to the lack of percolation path, which was greatly improved by the calendering process. Moreover, the dispersion of Ag NWs was analyzed with addition of PVP in terms of density and molecular weight. The excellent dispersion led to uniform distribution of Ag NWs in a cTCF. The continuous patterning was conducted using an embossed pattern roll to perform selective calendering. To evaluate the capability of the calendering process, various line widths and spacing patterns were investigated. The minimum pattern dimensions achievable were determined to be a line width of 0.1 mm and a line spacing of 1 mm. Finally, continuous patterning using selective calendering was applied to the fabrication of a flexible heater and a resistive touch sensing panel as flexible electronic devices to demonstrate its versatility.