55 results on '"Pravadelli, G."'
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2. Optimization of Assertion Placement in Time-Constrained Embedded Systems.
3. EFSM-based model-driven approach to concolic testing of system-level design.
4. Mutation analysis for SystemC designs at TLM.
5. UNIVERCM: The UNIversal VERsatile computational model for heterogeneous embedded system design.
6. Vacuity analysis for property qualification by mutation of checkers.
7. RTOS-aware refinement for TLM2.0-based HW/SW designs.
8. Effective EFSM generation for HW/SW-design verification.
9. DDPSL: An easy way of defining properties.
10. Semi-formal functional verification by EFSM traversing via NuSMV.
11. On the Functional Qualification of a Platform Model.
12. The impact of EFSM composition on functional ATPG.
13. On the Mutation Analysis of SystemC TLM-2.0 Standard.
14. Correct-by-construction generation of device drivers based on RTL testbenches.
15. Functional qualification of TLM verification.
16. RTL-TLM equivalence checking based on simulation.
17. An optimized CLP-based technique for generating propagation sequences.
18. Automatic generation of EFSMs and HLDDs for functional ATPG.
19. A Mutation Model for the SystemC TLM 2.0 Communication Interfaces.
20. Vacuity Analysis by Fault Simulation.
21. The role of parallel simulation in functional verification.
22. A CLP-Based Functional ATPG for Extended FSMs.
23. Towards Equivalence Checking Between TLM and RTL Models.
24. FATE: a Functional ATPG to Traverse Unstabilized EFSMs.
25. A methodology for abstracting RTL designs into TL descriptions.
26. On the Evaluation of Transactor-based Verification for Reusing TLM Assertions and Testbenches at RTL.
27. A TLM Design for Verification Methodology.
28. An Integrated Design and Verification Methodology for Reconfigurable Multimedia Systems.
29. Coverage of formal properties based on a high-level fault model and functional ATPG.
30. A Pseudo-Deterministic Functional ATPG based on EFSM Traversing.
31. Functional verification of networked embedded systems.
32. On the use of a high-level fault model to analyze logical consequence of properties.
33. A timing-accurate HW/SW cosimulation of an ISS with SystemC.
34. At-speed functional verification of programmable devices.
35. Functional verification based on the EFSM model.
36. Functional fault coverage: the chamber of secrets or an accurate estimation of gate-level coverage?
37. Redundant functional faults reduction by saboteurs synthesis [logic verification].
38. On the use of a high-level fault model to check properties incompleteness.
39. A SystemC-based framework for properties incompleteness evaluation.
40. An error simulation based approach to measure error coverage of formal properties.
41. A 1000X speed up for properties completeness evaluation.
42. AMLETO: a multi-language environment for functional test generation.
43. Improving high-level and gate-level testing with FATE: A functional automatic test pattern generator traversing unstabilised extended FSM.
44. HIFSuite: Tools for HDL code conversion and manipulation.
45. Interactive presentation abstract: Reusing of properties after discretization of hybrid automata.
46. Interactive presentation abstract: Assertion-based verification in embedded-software design.
47. Improving gate-level ATPG by traversing concurrent EFSMs.
48. Mapping Spiking Neural Networks on Multi-core Neuromorphic Platforms: Problem Formulation and Performance Analysis
49. Wearables, sensors, and smart devices for the detection and monitoring of chemotherapy-induced peripheral neurotoxicity: Systematic review and directions for future research.
50. Toward a Wearable System for Predicting Freezing of Gait in People Affected by Parkinson's Disease.
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