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When the dense pin-fins array distributed uniformly is used to dissipate the non-uniform heat source, it is easy to generate excessive cooling at the non-hot spot, which leads to unnecessary heat dissipation loss. In this study, a three-dimensional model of a multi-core chip-microchannel heat sink is established. Fin layout in the chip-microchannel is optimized under the conditions of non-uniform power-partition chip based on constructal theory. The total volume of fins in a channel is selected as the constraint condition. A genetic algorithm is used to seek the optimal construct. Comparing the optimal fin layout with the dense pin-fins array, the results demonstrate that the maximum temperature can be reduced by 6.75 K when Re number is 750, and the total pressure loss can be reduced by 54.1% when Re number is 750. Namely, under the condition of non-uniform heat source, the fins with a certain total volume were distributed reasonably, which can maintain the optimal balance of heat dissipation capacity and heat dissipation cost, so that the accurate and efficient thermal design is realized, and the better comprehensive benefits are obtained.

The layout of power modules is one of the key points in power module design, especially for silicon carbide module, which may parallel more devices compared with silicon counterpart. In this paper, along with the design example, a improved layout design method for planar power modules is presented. Some practical considerations and implementations are also introduced in the optimization of module layout design.

In this work, the properties of solvent and solvent-free electrically conductive adhesives (ECAs) in four curing manners and after solder reflows are investigated for multi-chip module applications. The curing behaviors and thermal degradation of solvent and solvent-free ECAs are also studied by differential scanning calorimeter and thermogravimetric analysis, respectively. The bulk resistivity of ECAs in four curing manners is significantly different, even if they are cured at the same temperature and time. The conductive trends of solvent and solvent-free ECAs are also different. The good and poor conductive properties of solvent ECA are obtained at curing temperature starting from room temperature and setting temperature, respectively. However, the results of solvent-free ECA are opposite. All the bulk resistivity and the coefficients of thermal expansion of solvent and solvent-free ECAs tend to decrease after solder reflows. The reasons are studied by thermomechanical analyzer, thermogravimetric analysis, topography and deformation measurement, and scanning electron microscopy. [ABSTRACT FROM AUTHOR]

This work describes the circuit and physical design implementation of the processor chip (CP), level-4 cache chip (SC), and the multi-chip module at the heart of the EC12 system. The chips were implemented in IBM's high-performance 32nm high-k/metal-gate SOI technology. The CP chip contains 6 super-scalar, out-of-order processor cores, running at 5.5 GHz, while the SC chip contains 192 MB of eDRAM cache. Six CP chips and two SC chips are mounted on a high-performance glass-ceramic substrate, which provides high-bandwidth, low-latency interconnections. Various aspects of the design are explored in detail, with most of the focus on the CP chip, including the circuit design implementation, clocking, thermal modeling, reliability, frequency tuning, and comparison to the previous design in 45nm technology. [ABSTRACT FROM PUBLISHER]

Abstract: The aim of this article is to provide a systematic method to perform optimization design for chip placement of multi-chip module in electronic packaging. Based on the investigation of the structural and thermal characteristics of multi-chip module, the key performance indexes of multi-chip module that include the lowest internal temperature objective, thermal-transfer accuracy, chip placement are analyzed. A hybrid model is presented by using genetic algorithm and response surface methodology for optimization. Furthermore, some design processes for improving the performance are induced. Finally, an example is discussed to apply the method. [Copyright &y& Elsevier]

Superconducting single flux quantum (SFQ) technology is well known for digital logic operations below 4.2K, which are compatible with the Josephson junction qubit. Operation speed and signal sensitivity of circuits in SFQ are also sufficient to control qubits. Therefore, the SFQ circuit is a candidate technology for multiple qubit control. However, the self-heating effect of the SFQ circuit is a potential barrier to development of an SFQ-supported multiple qubit system because the qubit operating temperature is lower than the conventional 4.2 K. The multi-chip approach is a possible solution because the qubit chip can be thermally isolated from the SFQ circuitry. We report on recent progress in SFQ circuit and packaging technology for operation at sub-Kelvin temperatures. As for multi-chip module technology, a test sample of the multi-chip module shows good reliability of electrical connections between chips, and each solder bump has a bandwidth wide enough for signal transmission. We have designed lower power SFQ circuits for sub-Kelvin temperatures. The critical currents of Josephson junctions were scaled down, inductances were scaled up, and bias voltage was reduced to make power consumption lower. Based on our fabrication technology, critical current densities were optimized by considering trade-off relations between fabrication availability and operation speed. We successfully confirmed its correct operations at around 0.35 K. The combination of the multi-chip module and optimized SFQ circuits is very effective way of controlling qubit. [ABSTRACT FROM AUTHOR]

We report experimental results for chip-to-chip data communications on a superconducting Multi-Chip-Module (MCM) using a novel fabrication technique. The MCM was produced using a non-conductive adhesive to bond a 5-mm x 5-mm test chip to a 1-cm x 1-cm carrier. To our knowledge, this is the first time this technique was used for MCM assembly at cryogenic temperatures. The module demonstrated superior mechanical stability and protection from its environment during thermal cycling. The MCM also retained its electrical properties after multiple thermal cycling from room temperature to 4 K. We designed test circuits including various digital test benches, as well as analog test structures for bump characteristics. The superconducting circuitry successfully passed single-flux quanta at rates exceeding 50 Gbps. We measured error rates lower than 5 x 10-14 at 36Gbps using 100-micrometer-diameter In-Sn solder bumps, and lower than 6 x 10-14 at 57Gbps using 30-micrometer-diameter solder bumps. [ABSTRACT FROM AUTHOR]

We report on development of a cryocooled system prototype for high-throughput single flux quantum (SFQ) digital applications. The system was designed to have 32 I/O links with a bandwidth of 10 Gbps/port. An SFQ multi-chip module (MCM), double mu-metal magnetic shields, a 40-K radiation shield, customized GaAs cryogenic amplifiers, a 32-pin wide-bandwidth cryo-probe, and 32 I/O cables were packaged in a vacuum chamber together with a two-stage 4-K 1-W Gifford-McMahon (G-M) cryocooler. S-parameter measurements showed that the analog bandwidth of the 1/0 link was 23 GHz. We demonstrated high-speed cryocooled operation of a test module, in which a 5 mm x 5 mm SFQ circuit chip was flip-chip bonded on a 16 mm x 16 mm MCM carrier with Φ30 μm InSn bump bonds, at bit rates up to 12.5 Gbps. Measured bit error rate (BER) was less than 10-12 for a 1023 - 1 pseudorandom bit sequence (PRBS) at 10 Gbps. [ABSTRACT FROM AUTHOR]

Abstract: This paper studies the elevated-temperature sweep characteristics of wire bond during the transfer molding process for semiconductor packages. The material properties of gold wire are obtained experimentally at various temperatures. A set of sweep experiments is also performed to acquire the sweep stiffness of wire bond for several bond spans and bond heights. The linearity of the load–transverse displacement curves from sweep experiments indicates that the ranges of the allowance bond pitch in most semiconductor packages may be within linear elasticity limits. The elastic numerical analysis may be applied to predict the sweep behavior of the wire bond. In order to predict the elevated temperature behavior of wire bond sweep, a methodology is proposed in this study. With the aids of geometry factor defined in Eq. and the three drag force models, Lamb’s, Sherman’s and Takaisi’s, the predictions of the elevated-temperature sweep deflections of wire bond can be tested. The results show that the increase of the sweep deflections is more related to bond span than bond height. [Copyright &y& Elsevier]

The influence of the substrate technology, assembly method, and housing material on the thermal, thermo-mechanical and cost performance of a radar module for automotive applications has been studied to address the product reliability aspects during the design phase. Flip chip and wire bonding have been evaluated for Multi-Chip Module—Laminate/Deposition (MCM-L/D) and Multi-Chip Module—Deposition (MCM-D) substrate technologies used for electronic packaging solutions in a harsh environment. Solder ball and direct attachment have been investigated as second-level assembly. As a result of thermal and thermo-mechanical simulations and cost analysis, radar module designs combining MCM-D and MCM-L/D with wire bonding have been revealed, which are preferable for use in different temperature environments with respect to two performance criteria, the maximum junction temperature and the manufacturing cost. Simulation-based guidelines have been developed for designing radar modules used in automotive applications while satisfying temperature and stress constraints provided for the module. Copyright © 2004 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

A prototype multi-chip hybrid pixel detector has been developed, based on tiling together eight Medipix2 readout chips onto a single Silicon sensor with a sensitive area of 28×56 mm2, for a total of about 0.5 Megapixels.One main difficulty of this approach is the high density of interconnections, needed to read out all the circuits in such a tiled multi-chip array. The level of connectivity between the readout circuits is drastically reduced by the use of a high-speed serial protocol, allowing the use of Low-Voltage Differential Signalling (LVDS) at frequencies above 100 MHz.To mount the multi-chip hybrid, we are using a new high-density printed-wire-board technology called “multi-layer build-up with staggered micro-vias” to accommodate the 128 wire-bonds per chip on a nine-layer printed wire board, with a smallest feature size of 60 μm line width, and a pitch of 110 μm. This accuracy is maintained over a board size of 110×55 mm2. [Copyright &y& Elsevier]

The objective of this study is to evaluate the use of several analytical compact heat transfer models for thermal design, optimization, and performance evaluation in electronic packaging. A model for heat spreading in orthotropic materials is developed. The developed model is used in conjunction with the other available heat transfer models in a resistance network for calculation of heat transfer rate and junction temperatures in a multi-chip module (MCM). Refrigeration cooled MCM of an IBM server is used to illustrate the methodology. Results of the analytical model and resistance network analysis are compared with a numerical solution. Capability of the analytical model in predicting the thermal field is discussed and effectiveness of using the analytical models in thermal design and optimization of electronic packages is demonstrated. [Copyright &y& Elsevier]

A new concept of 3D-electronic packaging is presented: Si-on-Si multi-chip module flip-chip technology with arrays of fine etched and filled vertical electrical interconnections (vias). Arrays of vias with a high number of interconnections, and not only peripheral interconnections are used. A 3D Si-on-Si stack package demonstrator has been realized consisting of four Si-substrates each representing a system level and containing four thinned and flip-chip assembled chips. The chips are flip-chip mounted on the flat side of the Si-substrates. When interconnecting the Si-substrates by bump technology the chips submerge into cavities on the rear side of the adjacent Si-substrate. The chips also test the technology and quality of the electronic packaging, and therefore contain a set of thin film heaters, junctions for temperature measuring, Al-meanders for stress and strain measuring and daisy chains for conduction path monitoring. [ABSTRACT FROM AUTHOR]

The thermal-flow-stress coupling model of multi-chip module with uniform heat generation under natural convection condition is established. Taking the chip aspect ratio and edge distance as design variables, a comprehensive performance indicator considering the maximum temperature, maximum thermal stress and maximum deformation is constructed to optimize the layout of chips with the constraints of the total occupied areas of printed circuit board and chips according to constructal theory. The results show that the comprehensive performance indicator decreases monotonically with the increase of the chip aspect ratio under the constraints of equal spacing, hence the chips should be designed as thin as possible according to the design requirements. Releasing the constraint of equal spacing, the comprehensive performance indicator increases monotonically with the increase of the edge distance when the chip aspect ratio is constant; the comprehensive performance indicator first decreases and then increases with the increase of chip aspect ratio when the edge distance is constant. The comprehensive performance indicator of the multi-chip module can be reduced by 0.65, the maximum temperature, the maximum thermal stress and the maximum deformation can be reduced by 6.28%, 9.44% and 9.66%, respectively. The methods and results herein could provide theoretical guidance for the thermal design of layout of multi-chip module. • The multi-physical field coupling simulation with finite element method is employed. • The designs with single degree-of-freedom and two degree-of-freedom are performed. • The maximums of temperature, thermal stress and deformation are considered. • The comprehensive thermal reliability of multi-chip module can be improved. [ABSTRACT FROM AUTHOR]

This paper presents advanced data collection methods using boundary scan based vector analysis, developed to debug manufacturing defects on cell based IC's such as JTAG compliant dice. Advantageously, they provide solutions to unknown dice by arranging identically designed Multi-chip Modules (MCM), to thereby diagnose possible flaws on dice due to thermal stresses on substrates as well as cold or hot soldering of the bumps, of which introducing fatigue and cracks, etc., defectives, and this system potentially to repair the problematic MCMs after trouble-shooting the twin-MCMs through self and mutual testing to validate the Known Good Dice (KGD). [ABSTRACT FROM AUTHOR]

As an architecture for a large-scale tera bit/s class ATM switch system, a building-block structure combining multiple small-scale switches (AHM: ATM circuit handling module) and interconnection switches (AMC: ATM intermodule connector) is proposed in this paper. In this proposed structure, mesh-like VP connections are made between AHMs by AMCs. Resource management is not done inside the AMC, but is simply executed inside AHMs which interconnect the AMCs. Resources are managed by the total capacity of connectivity (GVP: grouped virtual path) between the AHM and the input/output side AHM. It is shown theoretically that, with this proposed structure, it is possible to increase effectively the switching capacity in proportion to the number of AHMs connected. A new switch architecture with 160 Gb/s switch throughput is also proposed for application to the large-scale ATM switch system proposed in this paper. The proposed switch is an internal speed-up crossbar ATM switch which is suitable for switching high-speed cells. In order to avoid loss of QoS (Quality Of Service) of cells switched by AMC, it accommodates cells which are accelerated up to 10 Gb/s at the output port of the input side AHM. A new high-speed arbitration control algorithm which is distributed to each output line is adopted in this structure. The proposed control algorithm, in which a logical ring is composed of three buses, has a capability twice that of a conventional ring arbiter can realize very high switching throughput above 160 Gb/s. It is shown that a prototype ATM switch has been developed successfully using a combination of new technologies such as a new switch architecture, high-speed Si-bipolar LSI, and a sophisticated multi-chip module technology, and its functions and performance were satisfactorily confirmed. © 1997 Scripta Technica, Inc. Electron Comm Jpn Pt 1, 80(9): 68–79, 1997 [ABSTRACT FROM AUTHOR]

This paper provides a survey of MCM substrate test techniques. Test techniques that are based on capacitance,resistance, electron beam, latent opens, time domain network analysis(TDNA) and RF resonator are discussed. In this paper, test techniquesare applied to interconnect testing. [ABSTRACT FROM AUTHOR]