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The resistive switching properties of HfO2 based 1T-1R memristive devices are electrically modified by adding ultra-thin layers of Al2O3 into the memristive device. Three different types of memristive stacks are fabricated in the 130 nm CMOS technology of IHP. The switching properties of the memristive devices are discussed with respect to forming voltages, low resistance state and high resistance state characteristics and their variabilities. The experimental I–V characteristics of set and reset operations are evaluated by using the quantum point contact model. The properties of the conduction filament in the on and off states of the memristive devices are discussed with respect to the model parameters obtained from the QPC fit.

International audience; Highly polar materials are usually preferred over weakly polar ones to study strong electron–phonon interactions and its fascinating properties. Here, we report on the achievement of simultaneous confinement of charge carriers and phonons at the vicinity of a 2D vertical homovalent singularity (antiphase boundary, APB) in an (In,Ga)P/SiGe/Si sample. The impact of the electron–phonon interaction on the photoluminescence processes is then clarified by combining transmission electron microscopy, X-ray diffraction, ab initio calculations, Raman spectroscopy, and photoluminescence experiments. 2D localization and layer group symmetry properties of homovalent electronic states and phonons are studied by first-principles methods, leading to the prediction of a type-II band alignment between the APB and the surrounding semiconductor matrix. A Huang–Rhys factor of 8 is finally experimentally determined for the APB emission line, underlining that a large and unusually strong electron–phonon coupling can be achieved by 2D vertical quantum confinement in an undoped III–V semiconductor. This work extends the concept of an electron–phonon interaction to 2D vertically buried III–V homovalent nano-objects and therefore provides different approaches for material designs, vertical carrier transport, heterostructure design on silicon, and device applications with weakly polar semiconductors.

In this paper we have deposited structures comprising a stack of 10 periods made of 15 nmthick Ge multi quantum well (MQW) enclosed in 15 nm-thick Si0.2Ge0.8 barrier have been deposited on SiGe virtual substrates (VS) featuring different Ge contents in the 85% - 100% Ge range to investigate the influence of heteroepitaxial strain on the Si0.2Ge0.8 and Ge growth. With increasing Ge concentration of the VS, growth rate of the Si0.2Ge0.8 in the MQW increases. Si incorporation into the Si0.2Ge0.8 layer becomes also slightly higher. However, almost no influence of the growth rate is observed for Ge growth in the MQW. We argue that the increased tensile strain promotes the Si reaction at the surface. In the case of the Si0.2Ge0.8 growth on Ge, we observe a smeared interface due to the Ge segregation during the growth. Furthermore, we observe that this interface width increases with increasing Ge concentration of VS. We attribute this observation to the increased segregation of Ge driven by the increased strain energy accumulated in the in the Si0.2Ge0.8 layers. We also observed that the MQW layer “filters-out” threading dislocations formed in the VS.

Materials Research Letters 7(3), 117 - 123 (2019). doi:10.1080/21663831.2018.1561535, The HfO2-based resistive random access memory (RRAM) is one of the most promising candidatesfor non-volatile memory applications. The detection and examination of the dynamic behavior ofoxygen ions/vacancies are crucial to deeply understand the microscopic physical nature of theresistive switching (RS) behavior. By using synchrotron radiation based, non-destructive and bulksensitivehard X-ray photoelectron spectroscopy (HAXPES), we demonstrate an operando diagnosticdetection of the oxygen ‘breathing’ behavior at the oxide/metal interface, namely, oxygen migrationbetween HfO2 and TiN during different RS periods. The results highlight the significance ofoxide/metal interfaces in RRAM, even in filament-type devices., Published by Taylor & Francis, London [u.a.]

Buried-channel semiconductor heterostructures are an archetype material platform for the fabrication of gated semiconductor quantum devices. Sharp confinement potential is obtained by positioning the channel near the surface; however, nearby surface states degrade the electrical properties of the starting material. Here, a 2D hole gas of high mobility (5 × 105 cm2 V−1 s−1) is demonstrated in a very shallow strained germanium (Ge) channel, which is located only 22 nm below the surface. The top-gate of a dopant-less field effect transistor controls the channel carrier density confined in an undoped Ge/SiGe heterostructure with reduced background contamination, sharp interfaces, and high uniformity. The high mobility leads to mean free paths ≈ 6 µm, setting new benchmarks for holes in shallow field effect transistors. The high mobility, along with a percolation density of 1.2 × 1011cm−2, light effective mass (0.09me), and high effective g-factor (up to 9.2) highlight the potential of undoped Ge/SiGe as a low-disorder material platform for hybrid quantum technologies.

We provide an in-depth characterization of the dislocation distribution in partially relaxed Si0.92Ge0.08/Si(001) films. This is achieved by an innovative and general method, combining two state-of-the-art characterization techniques through suitable modeling. After having inferred the dislocation positions from transmission-electron-microscopy images, we theoretically reproduce scanning-x-ray-diffraction-microscopy tilt maps measured on the very same region of the sample. We obtain a nearly perfect match between model predictions and experimental data. As a result, we claim that it is possible to establish a local, direct correlation between the dislocations revealed by the transmission-electron-microscopy analysis and the measured lattice tilt distribution.

Resistive random access memories (RRAM) require high density, low power consumption and high reliability. Systematic statistic electrical, material and theoretical studies were demonstrated in this work to point out and clarify a key impact of carbon residues on the resistive switching (RS), particularly the endurance, of the integrated HfO2-based 4 kbit RRAM array. The mechanism of the carbon atoms interacting with oxygen vacancies and serving also as filament was understood in nanoscale by performing density functional theory (DFT) calculations. Under an oxygen-deficient environment, carbon atoms tend to fill in oxygen vacancy (VO··) sites and could form conductive filaments which require higher energy to be broken compared to the original VO·· filaments. By controlling the residual carbon concentration lower than 4%, highly reliable HfO2-based integrated 4 kbit RRAM array was achieved, which is of great interest for future nonvolatile memories.

Improvement of the photoluminescence (PL) of Phosphorus (P) doped Ge by P atomic layer doping (ALD) is investigated. Fifty P delta layers of 8 ×1013 cm-2 separated by 4 nm Ge spacer are selectively deposited at 300 °C on a 700 nm thick P-doped Ge buffer layer of 1.4 × 1019 cm-3 on SiO2 structured Si (100) substrate. A high P concentration region of 1.6 × 1020 cm-3 with abrupt P delta profiles is formed by the P-ALD process. Compared to the P-doped Ge buffer layer, a reduced PL intensity is observed, which might be caused by a higher density of point defects in the P delta doped Ge layer. The peak position is shifted by ∼0.1 eV towards lower energy, indicating an increased active carrier concentration in the P-delta doped Ge layer. By introducing annealing at 400 °C to 500 °C after each Ge spacer deposition, P desorption and diffusion is observed resulting in relatively uniform P profiles of ∼2 × 1019 cm-3. Increased PL intensity and red shift of the PL peak are observed due to improved crystallinity and higher active P concentration.

The integration of dislocation-free Ge nano-islands was realized via selective molecular beam epitaxy on Si nano-tip patterned substrates. The Si-tip wafers feature a rectangular array of nanometer sized Si tips with (001) facet exposed among a SiO2 matrix. These wafers were fabricated by complementary metal-oxide-semiconductor (CMOS) compatible nanotechnology. Calculations based on nucleation theory predict that the selective growth occurs close to thermodynamic equilibrium, where condensation of Ge adatoms on SiO2 is disfavored due to the extremely short re-evaporation time and diffusion length. The growth selectivity is ensured by the desorption-limited growth regime leading to the observed pattern independence, i.e. the absence of loading effect commonly encountered in chemical vapor deposition. The growth condition of high temperature and low deposition rate is responsible for the observed high crystalline quality of the Ge islands which is also associated with negligible Si-Ge intermixing owing to geometric hindrance by the Si nano-tip approach. Single island as well as area-averaged characterization methods demonstrate that Ge islands are dislocation-free and heteroepitaxial strain is fully relaxed. Such well-ordered high quality Ge islands present a step towards the achievement of materials suitable for optical applications., Scientific Reports, 6, ISSN:2045-2322

The integration of germanium (Ge) into silicon-based microelectronics technologies is currently attracting increasing interest and research effort. One way to realize this without threading and misfit dislocations is the so-called nanoheteroepitaxy approach. We demonstrate that a modified Si nanostructure approach with nanopillars or bars separated by TEOS SiO2 can be used successfully to deposit SiGe dots and lines free of misfit dislocations. It was found that strain relaxation in the pseudomorphically grown SiGe happens fully elastically. These studies are important for the understanding of the behavior of nanostructured Si for the final goal of Ge integration via SiGe buffer.

With the continuous scaling of resistive random access memory (RRAM) devices, in-depth understanding of the physical mechanism and the material issues, particularly by directly studying integrated cells, become more and more important to further improve the device performances. In this work, HfO2-based integrated 1-transistor-1-resistor (1T1R) RRAM devices were processed in a standard 0.25 μm complementary-metal-oxide-semiconductor (CMOS) process line, using a batch atomic layer deposition (ALD) tool, which is particularly designed for mass production. We demonstrate a systematic study on TiN/Ti/HfO2/TiN/Si RRAM devices to correlate key material factors (nano-crystallites and carbon impurities) with the filament type resistive switching (RS) behaviours. The augmentation of the nano-crystallites density in the film increases the forming voltage of devices and its variation. Carbon residues in HfO2 films turn out to be an even more significant factor strongly impacting the RS behaviour. A relatively higher deposition temperature of 300 °C dramatically reduces the residual carbon concentration, thus leading to enhanced RS performances of devices, including lower power consumption, better endurance and higher reliability. Such thorough understanding on physical mechanism of RS and the correlation between material and device performances will facilitate the realization of high density and reliable embedded RRAM devices with low power consumption.

A key factor for controlling Sn migration during GeSn deposition at a high temperature of 400 °C was investigated. Calculated results with a simple model for the Sn migration and experimental results clarified that low-deposition-speed (v d) deposition with v d’s of 0.68 and 2.8 nm/min induces significant Sn precipitation, whereas high-deposition-speed (v d = 13 nm/min) deposition leads to high crystallinity and good photoluminescence spectrum of the GeSn layer. These results indicate that v d is a key parameter, and that control of Sn migration at a high temperature is possible. These results are of great relevance for the application of high-quality Sn-based alloys in future optoelectronics devices.

In this work, we demonstrate the growth of Ge crystals and suspended continuous layers on Si(001) substrates deeply patterned in high aspect-ratio pillars. The material deposition was carried out in a commercial reduced-pressure chemical vapor deposition reactor, thus extending the "vertical-heteroepitaxy" technique developed by using the peculiar low-energy plasma-enhanced chemical vapor deposition reactor, to widely available epitaxial tools. The growth process was thoroughly analyzed, from the formation of small initial seeds to the final coalescence into a continuous suspended layer, by means of scanning and transmission electron microscopy, X-ray diffraction, and μ-Raman spectroscopy. The preoxidation of the Si pillar sidewalls and the addition of hydrochloric gas in the reactants proved to be key to achieve highly selective Ge growth on the pillars top only, which, in turn, is needed to promote the formation of a continuous Ge layer. Thanks to continuum growth models, we were able to single out the different roles played by thermodynamics and kinetics in the deposition dynamics. We believe that our findings will open the way to the low-cost realization of tens of micrometers thick heteroepitaxial layer (e.g., Ge, SiC, and GaAs) on Si having high crystal quality.

Here, we present a reliable process to deposit transparent conductive films on silicon oxide, quartz, and sapphire using a solid carbon source. This layer consists of partially ordered graphene flakes with a lateral dimension of about 5 nm. The process does not require any catalytic metal and exploits a high current arc evaporation (Φ-HCA) to homogeneously deposit a layer of carbon on heated substrates. A gas atmosphere consisting of Argon or Argon/Hydrogen blend acting as a buffer influences the morphology of the growing film. scanning tunneling microscopy, transmission electron microscopy, and Raman spectra were used for a thorough characterization of the samples in order to optimize the growth parameters. The best carbon layers have a surface resistance of 5.7 × 103 Ω◻ whereas the optical transparency of the coatings is 88% with an excellent homogeneity over areas of several cm2. Such results are compatible with most semiconductor fabrication processes and make this method very promising for various industrial applications.

The local electronic and atomic structure of (111)-oriented, single crystalline mixed Ce1-xPrxO2-delta (x = 0, 0.1 and 0.6) epitaxial thin films on silicon substrates have been investigated in view of engineering redox properties of complex oxide films. Non-destructive X-ray absorption near edge structure reveals that Pr shows only +3 valence and Ce shows only nominal +4 valence in mixed oxides. Extended x-ray absorption fine structure (EXAFS) studies were performed at K edges of Ce and Pr using a specially designed monochromator system for high energy measurements. They demonstrate that the fluorite lattice of ceria (CeO2) is almost not perturbed for x = 0.1 sample, while higher Pr concentration (x = 0.6) not only generates a higher disorder level (thus more disordered oxygen) but also causes a significant reduction of Ce-O interatomic distances. The valence states of the cations were also examined by techniques operating in highly reducing environments: scanning transmission electron microscopy-electron energy loss spectroscopy and X-ray photoemission spectroscopy; in these reducing environments, evidence for the presence of Ce3+ was clearly found for the higher Pr concentration. Thus, the introduction of Pr3+ into CeO2 strongly enhances the oxygen exchange properties of CeO2. This improved oxygen mobility properties of CeO2 are attributed to the lattice disorder induced by Pr mixing in the CeO2 fluorite lattice, as demonstrated by EXAFS measurements. Thus, a comprehensive picture of the modifications of the atomic and electronic structure of Ce1-xPrxO2-delta epitaxial films and their relation is obtained. (C) 2014 AIP Publishing LLC.

Among the many anticipated applications of graphene, some - such as transistors for Si microelectronics - would greatly benefit from the possibility to deposit graphene directly on a semiconductor grown on a Si wafer. We report that Ge(001) layers on Si(001) wafers can be uniformly covered with graphene at temperatures between 800{\deg}C and the melting temperature of Ge. The graphene is closed, with sheet resistivity strongly decreasing with growth temperature, weakly decreasing with the amount of deposited C, and reaching down to 2 kOhm/sq. Activation energy of surface roughness is low (about 0.66 eV) and constant throughout the range of temperatures in which graphene is formed. Density functional theory calculations indicate that the major physical processes affecting the growth are: (1) substitution of Ge in surface dimers by C, (2) interaction between C clusters and Ge monomers, and (3) formation of chemical bonds between graphene edge and Ge(001), and that the processes 1 and 2 are surpassed by CH$_{2}$ surface diffusion when the C atoms are delivered from CH$_{4}$. The results of this study indicate that graphene can be produced directly at the active region of the transistor in a process compatible with the Si technology.

Recently, the world’s fastest SiGe-HBT was presented by IHP researchers [1], which applies low ohmic nickel silicide (NiSi). Among other measures, this feature contributed to speed improvements. On the other hand, the integration of low-ohmic NiSi creates the risk for NiSi defects which could result in increased MOSFET leakage currents. The goal of this contribution is to find out from several two-step silicidations of Ni or NiPt layers a suitable process for a BiCMOS technology which enables low silicide RS for high cutoff frequencies of bipolar and MOS transistors without degradation of leakage currents. In result, a 300°C/450°C silicidation is proposed providing RS values of 3 to 4 Ω for both NiSi and NiPtSi. However, only the NiPtSi shows acceptable low leakage currents compared to NiSi. Therefore, NiPt extends the silicide process window for HBTs and MOSFETs. The phase transitions of Ni and NiPt silicides as a function of temperature are shown in Fig. 1, where the temperature range of the targeted NiSi phase is enlarged for NiPt compared to Ni. The investigated two-step NiSi formations are listed in Table 1. The NiPt layers were deposited in an Applied Materials laboratory. First, Ni2Si was formed by furnace anneal, low pressure anneals, or by a NiPt sputtering at 400°C. The Ni rich silicide was converted into NiSi by a second anneal at 450°C. The final Ni(Pt)Si sheet resistance (RS Ni(Pt)Si:1.+2.Ann) was tunable from 1.5 Ω to 10.5 Ω by the temperature and time of the first anneal (Fig. 2). At 300°C, the RS saturates at 3.3 Ω for 20 nm Ni and 1.6 Ω for 40 nm Ni, respectively. This indicates full Ni consumption. The furnace anneals at 200°C and 230°C do not show any RS saturation since Ni is consumed only partially. An RS increase for NiSi and NiPtSi on PSD (p source-drain) compared to NiSi on substrate is observed. One figure of merit of SiGe-HBTs is the maximum oscillation frequency fmax, which depends by the following equation fmax=sqrt(fT/(8πrBcBC)) on the transit frequency fT, the base resistance rB, and the collector-base capacitance cBC. A silicide resistance variation could mainly influence rB. In Fig. 3a, the sheet resistance of the silicided base polysilicon (RS BasePolySilicide) together with fmax of two HBT layouts are plotted for several silicide formations. It exists a correlation between fmax and RS BasePolySilicide, which is shown in Fig. 3b. In general, fmax could be enlarged by a silicide resistance reduction for special HBT layouts. For these low-ohmic and thick Ni(Pt)Si layers, special attention has to be paid to the MOSFET leakage currents, which can be enlarged by lateral silicide pipes towards the conducting channel or by defects along the SD – STI (shallow trench isolation) interface [2]. Another leakage current source are silicide spikes shortening in a perpendicular direction the SD and the well. Three types of P+Nwell and N+Pwell diodes are suitable to determine and distinguish these silicide based yield killers: area diodes to detect spikes, STI separated island diodes to recognize SD-STI defects, and diodes with long poly-gates on SD-well areas to determine pipes at gate edges. In result, the area and island diodes showed no leakage current increase for the studied silicidations, i.e. defects along the SD-STI edge and spikes are not critical here. The leakage currents of gate-edged diodes on N+Pwell and P+Nwell are presented in Fig.4. Both diode types show low leakage currents for the 200°C and 230°C anneals, because the low lateral silicidation at these temperatures reduces the probability for piping. At 300° the N+Pwell leakage current increases slightly up to 2x10-9A, but significantly up to 1x10-7A for the P+Nwell diode. This is a clear indication for pipes at the gate edges [3]. In contrast, almost no enhanced leakage current was observed for the NiPt silicidations with 200° to 300°C anneals. The pipe suppression of the NiPt silicide system might be caused by the Pt agglomeration at the silicide-SD interface [4]. The limits of the NiPt pipe suppression are shown for N+Pwell diodes silicidated with a NiPt deposition at 400°C. Leakage currents of 1x10-8A could indicate NMOS-typical pipes, as described by Yamaguchi [5]. In summary, silicide layers with low RS values of 3Ω to 4Ω were formed by two-step annealing of Ni and NiPt at 300°C and 450°C. These silicides support high fmax values of SiGe HBTs. However, only the NiPt silicide process provided acceptable low leakage currents of MOSFET test structures indicating an extended process capability of NiPtSi compared to NiSi. Figure 1