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The silicon‐based solar cell is one of the most important enablers toward high‐efficiency, low‐cost clean energy resources. Metallization of silicon‐based solar cells typically utilizes screen‐printed silver–aluminum (Ag–Al), which improves the cells′ electrical performance. To date, metal silicide‐based ohmic contacts are occasionally used as an alternative candidate only to the front‐contact grid lines in crystalline silicon (c‐Si)‐based solar cells. In this study, we investigate the electrical characteristics of nickel mono‐silicide (NiSi)/Cu–Al ohmic contact on the rear side of c‐Si solar cells. We observe a significant enhancement in the fill factor of approximately 6.5 % for NiSi/Cu–Al rear contacts, thereby leading to an increase in the efficiency by 1.2 % compared to Ag–Al. This is attributed to the improvement of the parasitic resistance in which the series resistance decreased by 0.737 Ω cm−2. Further, we complement experimental observation with a simulation of different contact resistance values, which shows the NiSi/Cu–Al rear contact to be a promising low‐cost metallization for c‐Si solar cells with enhanced efficiency. Silicide solution: Metal silicide‐based ohmic contacts are occasionally used as an alternative candidate only to the front contact grid lines in crystalline silicon (c‐Si)‐based solar cells. In this study, the authors investigate the electrical characteristics of nickel mono‐silicide (NiSi)/Cu–Al ohmic contact on the rear side of c‐Si solar cells compared to Ag–Al metallization. [ABSTRACT FROM AUTHOR]

We report a wavy channel (WC) architecture thin-film transistor-based digital circuitry using ZnO as a channel material. The novel architecture allows for extending device width by integrating vertical finlike substrate corrugations giving rise to 50% larger device width, without occupying extra chip area. The enhancement in the output drive current is 100%, when compared with conventional planar architecture for devices occupying the same chip area. The current increase is attributed to both the extra device width and 50% enhancement in field-effect mobility due to electrostatic gating effects. Fabricated inverters show that WC inverters can achieve two times the peak-to-peak output voltage for the same input when compared with planar devices. In addition, WC inverters show 30% faster rise and fall times, and can operate up to around two times frequency of the planar inverters for the same peak-to-peak output voltage. WC NOR circuits have shown 70% higher peak-to-peak output voltage, over their planar counterparts, and WC pass transistor logic multiplexer circuit has shown more than five times faster high-to-low propagation delay compared with its planar counterpart at a similar peak-to-peak output voltage. [ABSTRACT FROM AUTHOR]

High-performance thin film transistor (TFT) can be a great driving force for display, sensor/actuator, integrated electronics, and distributed computation for the Internet of Everything applications. While semiconducting oxides, such as zinc oxide (ZnO), present promising opportunity in that regard, still wide area of improvement exists to increase the performance further. Here, we show a wavy channel (WC) architecture for ZnO integrated TFT, which increases transistor width without chip area penalty, enabling high performance in material agnostic way. We further demonstrate digital logic NAND circuit using the WC architecture and compare it with the conventional planar architecture. The WC architecture circuits have shown $2\times $ higher peak-to-peak output voltage for the same input voltage. They also have $3\times $ lower high-to-low propagation delay times, respectively, when compared with the planar architecture. The performance enhancement is attributed to both extra device width and enhanced field-effect mobility due to higher gate field electrostatics control. [ABSTRACT FROM PUBLISHER]

Increased output current while maintaining low power consumption in thin-film transistors (TFTs) is essential for future generation large-area high-resolution displays. Here, we show wavy channel (WC) architecture in TFT that allows the expansion of the transistor width in the direction perpendicular to the substrate through integrating continuous fin features on the underlying substrate. This architecture enables expanding the TFT width without consuming any additional chip area, thus enabling increased performance while maintaining the real estate integrity. The experimental WCTFTs show a linear increase in output current as a function of number of fins per device resulting in \(3.5\times \) increase in output current when compared with planar counterparts that consume the same chip area. The new architecture also allows tuning the threshold voltage as a function of the number of fin features included in the device, as threshold voltage linearly decreased from 6.8 V for planar device to 2.6 V for WC devices with 32 fins. This makes the new architecture more power efficient as lower operation voltages could be used for WC devices compared with planar counterparts. It was also found that field effect mobility linearly increases with the number of fins included in the device, showing almost \(1.8\times \) enhancements in the field effect mobility than that of the planar counterparts. This can be attributed to higher electric field in the channel due to the fin architecture and threshold voltage shift. [ABSTRACT FROM PUBLISHER]

We demonstrate a new thin film transistor (TFT) architecture that allows expansion of the device width using continuous fin features - termed as wavy channel (WC) architecture. This architecture allows expansion of transistor width in a direction perpendicular to the substrate, thus not consuming extra chip area, achieving area efficiency. The devices have shown for a 13% increase in the device width resulting in a maximum 2.5× increase in 'ON' current value of the WCTFT, when compared to planar devices consuming the same chip area, while using atomic layer deposition based zinc oxide (ZnO) as the channel material. The WCTFT devices also maintain similar 'OFF' current value, ∼100 pA, when compared to planar devices, thus not compromising on power consumption for performance which usually happens with larger width devices. This work offers an interesting opportunity to use WCTFTs as backplane circuitry for large-area high-resolution display applications. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]

Towards pyrolysis oil commercialization: Solar energy is the key renewable energy source on earth. To harness the sunlight's energy, crystalline silicon solar cells are widely used due to their albeit moderate efficiency of 20 %, as they still provide the most reliable combination of performance and cost. To enhance the performance further, one key area is improvement in contact engineering for solar cells. By using a low‐resistivity contact material the overall current collection from the cell can be potentially enhanced. In this study, salicidation‐based, low‐cost ohmic contact engineering based upon CMOS technology is demonstrated to enhance the performance of silicon photovoltaic cells by nearly 2 %. The cover page illustrates the concept of improved contact engineering in crystalline silicon‐based solar cells for improved performance and reliable manufacturability. More details can be found in the Full Paper by Rabab R. Bahabry et al. on page 1627 in Issue 9, 2018 (10.1002/ente.201700790). [ABSTRACT FROM AUTHOR]

Hetero-structure tunnel junctions in non-planar gate-all-around nanowire (GAA NW) tunnel FETs (TFETs) have shown significant enhancement in 'ON' state tunnel current over their all-silicon counterpart. Here we show the unique concept of nanotube TFET in a hetero-structure configuration that is capable of much higher drive current as opposed to that of GAA NW TFETs.Through the use of inner/outer core-shell gates, a single III-V hetero-structured nanotube TFET leverages physically larger tunneling area while achieving higher driver current (ION) and saving real estates by eliminating arraying requirement. Numerical simulations has shown that a 10 nm thin nanotube TFET with a 100 nm core gate has a 5×normalized output current compared to a 10 nm diameter GAA NW TFET. [ABSTRACT FROM AUTHOR]

As shown by Hanna et al. (pp. 248–251), by gENerating a wavy architecture in classical transistor topology, high output currENt is achieved – opENing up bold futuristic opportunity for ultra ‐ high resolution bright display. Irrespective of the material choice – the unique architecture can provide exciting thin film transistor performance ENhancemENt.Hanna et al. demonstrate the advantage of using the wavy architecture in terms of area efficiENcy, higher output currENt, higher field ‐ effect mobility and similar OFF currENt levels and Ion/Ioff ratios compared to the planar counterparts for a thin film transistor fabricated with zinc oxide channel material. The low OFF currENt levels and high Ion/Ioff ratios for the wavy ‐ channel devices ENsure that standby power consumption remains similar to the planar counterparts, while improving the ON currENt values. This proves the significance of this new architecture for large ‐ area high ‐ resolution display applications. [ABSTRACT FROM AUTHOR]