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Recent studies show that peripheral circuit (including decoders, wordline drivers, input and output drivers) constitutes a large portion of the cache leakage. In addition, as technology migrates to smaller geometries, leakage contribution to total power consumption increases faster than dynamic power, indicating that leakage will be a major contributor to overall power consumption. This paper presents zig-zag share, a circuit technique to reduce leakage in SRAM peripherals by putting them into low-leakage power sleep mode. The zig-zag share circuit is further extended to enable multiple sleep modes for cache peripherals. Each mode represents a trade-off between leakage reduction and the wakeup delay. Using architectural control of multiple sleep modes, an integrated technique called MSleep-Share is proposed and applied in L1 and L2 caches. MSleep-share relies on cache miss information to guide leakage control mechanism and switch peripheral circuit's power mode. The results show leakage reduction by up to 40\times in deeply pipelined SRAM peripheral circuits, with small area overhead and small additional delay. This noticeable leakage reduction translates to up to 85% overall leakage reduction in on-chip memories. [ABSTRACT FROM AUTHOR]

Although triple modular redundancy (TMR) has been widely used to mitigate single event upsets (SEUs) in static random access memory-based field-programmable gate arrays (FPGAs), SEU-caused bridging faults between the triplicated modules do not guarantee the correctness of TMR designs under all SEUs. In this paper, we present a novel computer-aided design flow for redundancy-based applications on FPGAs in order to mitigate the impact of SEUs in the configuration bitstreams. We introduce the notions of modular redundancy conflicts and vulnerability-gap conflicts which maintain the fundamental assumption underlying the integrity of redundancy-based designs (i.e., self-containment of SEU-induced faults within a single replica of redundant resources). When the impact of SEU-induced bridging faults is considered in high-level synthesis as well as physical synthesis, on average more than 30% improvement in the number of potential SEU-induced bridging faults can be reached as well as improvements in the performance and area utilization, compared to post-synthesis TMR, in which the voters are applied to the feedback structures in the circuit. Compared to the extreme case of post-synthesis TMR in which the voters are applied at the end of every configurable logic block, we reach 38% (26%) improvement in performance(area) of the implemented circuits. [ABSTRACT FROM AUTHOR]

Abstract: Leakage power has grown significantly and is a major challenge in SoC design. Among SoC''s components, clock distribution network power accounts for a large portion of chip power. This paper proposes to deploy sleep transistor insertion (STI) in the clock tree of datapaths in ASICs or in general-purpose processors in order to reduce leakage power. It characterizes the effect of sleep transistor sharing and sizing on clock tree wakeup time, leakage power, and propagation delay. It then uses these characteristics during leakage power optimization. It describes a post synthesis sleep transistor insertion (PSSTI), a heuristic clustering algorithm for sleep transistor insertion with the objective of total power minimization in a given clock tree. Sleep transistor sharing and sizing are deployed in order to meet the clock skew and wakeup delay constraints. The potential benefits of STI in ASIC design are evaluated using a standard industrial VLSI-CAD flow including sleep-transistor insertion and routing after the clock synthesis and place-and-route of the benchmark circuits. The results show that the clock tree leakage power is reduced by 19–32% depending on the topology of the synthesized clock tree. We also apply PSSTI in the clock tree of the datapaths in general-purpose processors using architectural control of the sleep mode. This achieves a reduction in the leakage power and the dynamic power of the clock tree within different datapath components (adder, multiplier, etc.) of as much as 80%. This approach is also applicable to other on-chip structure where inverters are large in size and commonly used, e.g. SRAMs or networks-on-a-chip, which combined with the clock tree savings will significantly reduce processor or ASIC overall power consumption. [Copyright &y& Elsevier]