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The implementation of current deep learning training algorithms is power-hungry, due to data transfer between memory and logic units. Oxide-based resistive random access memories (RRAMs) are outstanding candidates to implement in-memory computing, which is less power-intensive. Their weak RESET regime is particularly attractive for learning, as it allows tuning the resistance of the devices with remarkable endurance. However, the resistive change behavior in this regime suffers from many fluctuations and is particularly challenging to model, especially in a way compatible with tools used for simulating deep learning. In this work, we present a model of the weak RESET process in hafnium oxide RRAM and integrate this model within the PyTorch deep learning framework. Validated on experiments on a hybrid CMOS/RRAM technology, our model reproduces both the noisy progressive behavior and the device-to-device (D2D) variability. We use this tool to train binarized neural networks (BNNs) for the MNIST handwritten digit recognition task and the CIFAR-10 object classification task. We simulate our model with and without various aspects of device imperfections to understand their impact on the training process and identify that the D2D variability is the most detrimental aspect. The framework can be used in the same manner for other types of memories to identify the device imperfections that cause the most degradation, which can, in turn, be used to optimize the devices to reduce the impact of these imperfections.

Phase-Change Memory (PCM) demonstrated to be a mature Non- Volatile Memory technology to address Storage Class Memory (SCM) applications that can be distinguished in memory-type (M-SCM) and storage-type (S-SCM). In this work, we present how aGeSbTe (aGST) alloy can address both SCM types, in particular using Si doping. Thanks to the electrical characterization of 4 kb PCM arrays, we show how Si doping in aGST helps tuning the crystallization dynamic during the programming operations, leading to highly reliable intermediate resistance states. We support our results by TEM analyses and finally we present improved multi-level cell (MLC) operations in Si-doped devices, achieved already with a simple double-step protocol. We demonstrate the aGST alloy suitability for SCM applications: undoped alloy allows targeting M-SCM thanks to its high endurance and high programming speed, whereas Si-doped aGST featuring MLC capability and improved data retention can address S-SCM specifications.

International audience; In this paper, we demonstrate at array level and in industrial like devices, the extreme scaling down to nanometric dimensions of the Phase-Change Memory technology thanks to an innovative Self-Nano-Confined PCM device (SNC PCM). We show how such solution based on an optimized GeN/GeSbTe stack enables programming down to 50 $\mu$A and endurance up to more than 10$^8$ cycles in 4 kb arrays, with the huge advantage of having no dependency on the critical lithography dimension used. We further demonstrate that the high thermal confinement achieved in such extremely confined PCM makes the engineering of the SET pulse becoming fundamental in order to assure a reduced SET resistance drift. Moreover, thanks to physico-chemical analyses and 3D TCAD electro-thermal simulations we demonstrate the Self-Nano-Confined phenomenon, revealing an effective scaling of the PCM down to around 12 nm and how it improves the thermal efficiency of the device thanks to a reduced current density and thermal stress in the system.

Hardware for deep neural network (DNN) inference often suffers from insufficient on-chip memory, thus requiring accesses to separate memory-only chips. Such off-chip memory accesses incur considerable costs in terms of energy and execution time. Fitting entire DNNs in on-chip memory is challenging due, in particular, to the physical size of the technology. Here, we report a DNN inference system—termed Illusion—that consists of networked computing chips, each of which contains a certain minimal amount of local on-chip memory and mechanisms for quick wakeup and shutdown. An eight-chip Illusion system hardware achieves energy and execution times within 3.5% and 2.5%, respectively, of an ideal single chip with no off-chip memory. Illusion is flexible and configurable, achieving near-ideal energy and execution times for a wide variety of DNN types and sizes. Our approach is tailored for on-chip non-volatile memory with resilience to permanent write failures, but is applicable to several memory technologies. Detailed simulations also show that our hardware results could be scaled to 64-chip Illusion systems. A networked system of eight computing chips, each with its own on-chip memory, can be used to efficiently implement a range of neural network models and sizes.

IEEE transactions on nuclear science 68(8), 1542 - 1547 (2021). doi:10.1109/TNS.2021.3085962, Published by IEEE, New York, NY

The design of systems implementing low precision neural networks with emerging memories such as resistive random access memory (RRAM) is a significant lead for reducing the energy consumption of artificial intelligence. To achieve maximum energy efficiency in such systems, logic and memory should be integrated as tightly as possible. In this work, we focus on the case of ternary neural networks, where synaptic weights assume ternary values. We propose a two-transistor/two-resistor memory architecture employing a precharge sense amplifier, where the weight value can be extracted in a single sense operation. Based on experimental measurements on a hybrid 130 nm CMOS/RRAM chip featuring this sense amplifier, we show that this technique is particularly appropriate at low supply voltage, and that it is resilient to process, voltage, and temperature variations. We characterize the bit error rate in our scheme. We show based on neural network simulation on the CIFAR-10 image recognition task that the use of ternary neural networks significantly increases neural network performance, with regards to binary ones, which are often preferred for inference hardware. We finally evidence that the neural network is immune to the type of bit errors observed in our scheme, which can therefore be used without error correction., Comment: arXiv admin note: substantial text overlap with arXiv:2005.01973

This paper presents an outlook of crosspoint memory arrays. We survey the characteristics, strengths and challenges of crosspoint array composed by a resistive memory device integrated in series with a back-end selector. We present the performances of our 1S1R technology composed of an HfO 2 OxRAM (1R) combined with a GeSeSbN based Ovonic Threshold Switch (1S). We benchmark our results with a detailed collection of experimental data reported in the literature.

The advent of deep learning has considerably accelerated machine learning development. The deployment of deep neural networks at the edge is however limited by their high memory and energy consumption requirements. With new memory technology available, emerging Binarized Neural Networks (BNNs) are promising to reduce the energy impact of the forthcoming machine learning hardware generation, enabling machine learning on the edge devices and avoiding data transfer over the network. In this work, after presenting our implementation employing a hybrid CMOS - hafnium oxide resistive memory technology, we suggest strategies to apply BNNs to biomedical signals such as electrocardiography and electroencephalography, keeping accuracy level and reducing memory requirements. We investigate the memory-accuracy trade-off when binarizing whole network and binarizing solely the classifier part. We also discuss how these results translate to the edge-oriented Mobilenet V1 neural network on the Imagenet task. The final goal of this research is to enable smart autonomous healthcare devices.

While Resistive Random Access Memories (RRAM) are perceived nowadays as a promising solution for the future of computing, these technologies suffer from intrinsic variability regarding programming voltage, switching speed and achieved resistance values. Write Termination (WT) circuits are a potential solution to solve these issues. However, previously reported WT circuits do not demonstrate sufficient reliability. In this work, we propose an industrially-ready WT circuit that was simulated with a RRAM model calibrated on real measurements. We perform extensive CMOS and RRAM variability simulations to extract the actual performances of the proposed WT circuit. Finally, we simulate the effects of the proposed WT circuit with memory traces extracted from real Edge-level data-intensive applications. Overall, we demonstrate 2× to 40× of energy gains at bit level. Moreover, we show from 1.9× to 16.2× energy gains with real applications running depending on the application memory access pattern thanks to the proposed WT circuit.

International audience; We demonstrate successful scalability of conventional 100µm diameter TiN/HZO/TiN capacitors down to 300nm by successfully co-integrating them for the first time in the Back-End-Of-Line of 130nm CMOS technology. Excellent performance are reported on those scaled bitcells, such as remnant polarization 2.PR > 40µC/cm², endurance > 10 11 cycles, switching speeds < 100ns, operating voltages < 4V, and data retention at 125°C. Presented results pave the way to < 10fJ/bit ultra-low power FeRAM for IoT applications.

Endurance reliability at the array level of resistive random access memories (RRAMs) is addressed. Both oxide based RAM and conductive bridge RAM stacks are extensively characterized, presenting various measurements over resistive layers, memory stacks, and programming conditions. These measurement results allow to extract the maximum number of cycles before breakdown $\text {N}_{c\,\text {max}}$ . It is found that this quantity follows a log-normal law. According to this first significant result, the impact of SET and RESET conditions on $\text {N}_{c\,\text {max}}$ statistics is studied. Using tailored ramp voltage stress (RVS) measurements, the minimum RRAM switching voltage is extracted along the endurance cycles and then correlated with the memory degradation. To explain and better understand all these experimental results, a stochastic model based on defect generation in a constriction zone of the resistive layer during cycling is proposed. After exploration of the size, geometry, and shape of such constriction zone, as well as different probability laws governing breakdown, modeled $\text {N}_{c\,\text {max}}$ distributions fitting the experimental ones are successfully generated and deeper explanations about the origin of the maximum number of cycles variability are inferred.

Brain-inspired architectures in neuromorphic hardware are currently subject to intensive research as an alternative to the limits of traditional computer organisation. The remarkable computing performance and efficiency of biological nervous systems are widely attributed to the co-localisation of memory and computation spatially throughout the structure. Moreover, it appears that a number of local self-organising neural mechanisms play their part in efficient biological computation. An example is neuronal intrinsic plasticity, where a neuron adapts its parameters to maximise its information capacity based on the statistical properties of its input while minimising the power it consumes. CMOS circuits implementing neuron models have been proposed but require their parameters to be set by biases originating from a centralised memory. In this work, we propose a hybrid CMOS-RRAM circuit that addresses this problem through storing neuron parameters within programmable nonvolatile resistive memories incorporated into the CMOS neuron. Additional circuits exploit the stochastic switching properties of resisitive memories to map a local intrinsic plasticity algorithm onto the proposed neuron. We demonstrate the computational advantages of this algorithm through simulation, calibrated on experimental data, whereby the neuron maximises its information capacity while minimising its power consumption, as is the case for biological neurons.

International audience; A clear comparison between Atomic Layer Deposition and Ion Implantation Si doping techniques is established. Comparable remnant polarization and coercive fields are obtained at lower Si content (%Si) for Ion Implantation, with a slight decrease of endurance performance. Switching signal engineering demonstrates a wide range of performance achievable with HfO2:Si ferroelectric layer.

International audience; Resistive random access memories (RRAM) are novel nonvolatile memory technologies, which can be embedded at the core of CMOS, and which could be ideal for the in-memory implementation of deep neural networks. A particularly exciting vision is using them for implementing Binarized Neural Networks (BNNs), a class of deep neural networks with a highly reduced memory footprint. The challenge of resistive memory, however, is that they are prone to device variation, which can lead to bit errors. In this work we show that BNNs can tolerate these bit errors to an outstanding level, through simulations of networks on the MNIST and CIFAR10 tasks. If a standard BNN is used, up to 10 −4 bit error rate can be tolerated with little impact on recognition performance on both MNIST and CIFAR10. We then show that by adapting the training procedure to the fact that the BNN will be operated on error-prone hardware, this tolerance can be extended to a bit error rate of 4 × 10 −2. The requirements for RRAM are therefore a lot less stringent for BNNs than more traditional applications. We show, based on experimental measurements on a RRAM Hf O2 technology, that this result can allow reduce RRAM programming energy by a factor 30.

Limited endurance of resistive RAM (RRAM) is a major challenge for future computing systems. Using thorough endurance tests that incorporate fine-grained read operations at the array level, we quantify for the first time temporary write failures (TWFs) caused by intrinsic RRAM cycle-to-cycle and cell-to-cell variations. We also quantify permanent write failures (PWFs) caused by irreversible breakdown/dissolution of the conductive filament. We show how technology-, RRAM programing-, and system resilience-level solutions can be effectively combined to design new generations of energy-efficient computing systems that can successfully run deep learning (and other machine learning) applications despite TWFs and PWFs. We analyze corresponding system lifetimes and TWF bit error ratio. Nanyang Technological University Accepted version This work was supported in part by Defense Advanced Research Projects Agency, in part by NSF-SRC/Nanoelectronics Research Initiative/Global Research Collaboration Energy-Efficient Computing: From Devices to Architectures, in part by STARnet SONIC, in part by NSF, in part by the Stanford SystemX Alliance, in part by NTU Startup Grant (M4082035), and in part by the AME Programmatic Hardware Software Co-Optimization for Deep Learning (M4070301). The review of this paper was arranged by Editor Y.-H. Shih. (Corresponding author: Mohamed M. Sabry.)

International audience; Resistive Memory (RRAM)-based Ternary Content Addressable Memories (TCAMs) were developed to reduce cell area, search energy and standby power consumption beyond what can be achieved by SRAM-based TCAMs. In previous works, RRAM-based TCAMs have already been fabricated, but the impact of RRAM reliability on TCAM performance has never been proven until now. In this work, we fabricated and extensively tested a RRAM-based TCAM circuit. We show that a trade-off exists between search latency and reliability in terms of match/mismatch detection and search/read endurance, and that a RRAM-based TCAM is an ideal building block in multi-core neuromorphic architectures. These ones would not be affected by long latency time and limited write endurance, and could greatly benefit from their high-density and zero standby power consumption.

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is one of the leading candidates for embedded memory convergence in advanced technology nodes. It is particularly adapted to low-power applications, requiring a decent level of performance. However, it also have interests for secured applications. The PRESENT cipher is a lightweight cryptographic algorithm targeting ultra-low power applications such as the Internet of Things or RFID. This paper aims to combine this low power cryptographic algorithm with the STT-MRAM which main feature is its low consumption. This new generation of ciphers is very interesting for normally-off applications. Actually, for these specific applications hybrid CMOS/STT-MRAM ciphers consume less power than pure CMOS cryptographic algorithms.Although the performance of STT-MRAM is much better than standard non-volatile technologies like flash, it suffers from limitations for high-speed applications. A new MRAM technology based on Spin-Orbit Torque (SOT) was recently discovered and offers better performance in terms of speed and endurance, at the expense of a slightly degraded density. In this paper, we also propose a comparative study of several architectures of SOT-MRAM memories for evaluating the possible advantages of this NV technology for high-speed applications.

International audience; Resistive switching memories (RRAMs) have attracted wide interest as adaptive synaptic elements in artificial bio-inspired Spiking Neural Networks (SNNs). These devices suffer from high cycle-to-cycle and cell-to-cell conductance variability, which is usually considered as a big challenge. However, biological synapses are noisy devices and the brain seems in some situations to benefit from the noise. It has been predicted that RRAM-based SNNs are intrinsically robust to synaptic variability. Here, we investigate this robustness based on extensive characterization data: we analyze the role of noise during unsupervised learning by Spike-Timing Dependent Plasticity (STDP) for detection in dynamic input data and classification of static input data. Extensive characterizations of multi-kilobits HfO 2-based Oxide-based RAM (OxRAM) arrays under different programming conditions are presented. We identify the trade-offs between programming conditions, power consumption, conductance variability and endurance features. Finally, the experimental results are used to perform system-level simulations fully calibrated on the experimental data. The results demonstrate that, similarly to biology, SNNs are not only robust to noise but a certain amount of noise can even improve the network performance. OxRAM conductance variability increases the range of synaptic values explored during the learning process. Moreover, the reduction of constraints on the OxRAM conductance variability allows the system to operate at low power programming conditions.

International audience; Spin Orbit Torque Magnetic RAM (SOT-MRAM) approach represents a new way to overcome over Spin Transfer Torque (STT) memory limitations by separating the reading and the writing paths. It is particularly interesting for high speed applications that do not require very high density because of two transistors per bit cell. This paper presents a high density SOTMRAM memory array based on a single transistor and a unidirectional diode. There are three advantages of this approach. The number of transistors for 32kb memory array is decreased by factor of 45% which leads to an improved cell density by 20% compared to conventional SOT bit cell. Moreover, it requires less control to read operation and finally high endurance, high speed and high density can be achieved. The key challenge going will be to adjust between sense margin and read energy

International audience; Phase change memory can provide a remarkable artificial synapse for neuromorphic systems, as it features excellent reliability and can be used as an analog memory. However, this approach is complicated by the fact that crystallization and amorphization differ radically: crystallization can be realized in a very gradual manner, very similarly to synaptic potentiation, while the amorphization process tends to be abrupt, unlike synaptic depression. Addressing this non-biorealism of amorphization requires system-level solutions that have considerable energy cost or limit the generality of the approach. This work demonstrates experimentally that an adaptation of the memory structure associated with an initialization electrical pulse followed by a sequence of identical fast pulses can overcome this challenge. A single device can then naturally implement gradual long-term potentiation and depression, much like synapses in biology. This study evidences through statistical measurements the reproducibility of the approach, discusses its physical origin, as well as the importance of the device architecture and of the initial electrical pulse. Through the use of system-level simulation, it is shown that this device is especially adapted to a neuroscience-inspired learning. These results highlight how nanodevices can be suitable for bioinspired applications while retaining the qualities of industrial technology.

International audience; In this paper, programming operations are optimizedfor low energy consumption and short latency time applicationsin RRAM kb arrays. Origin of consumption (role of pulse’stime, programming current and voltage in SET and RESEToperations) is quantified on HfO$_2$ oxide based RRAMtechnology. Specific patterns are evaluated to reduce latencytime and energy consumption in memory devices. Innovativecircuit with $on\ the\ fly$ switching detection is proposed, allowingto reduce programming consumption down to single pJoperation in large memory arrays.

International audience; In this letter, the fundamental variability limits of filament-based OxRRAM are investigated considering different transistor sizes and metal–insulator–metal (MIM) stacks featuring different materials and thicknesses. Cellto-cell variability is analyzed through an extensive characterization of Forming, Set, and Reset operations on 4-kb OxRRAM arrays. The results obtained in terms of switching voltage variability and resistance variability from cell-to-cell are compared and discussed to identify the variability limiting component as a function of the conduction regime and to understand the impact of transistor MIM stack parameters on variability and performances.

International audience; This paper presents an HfO2 based resistive switching memory (RRAM) in series with a GeSe-based Ovonic Threshold Switching (OTS) selector. Detailed investigation of the main memory operations, forming, set, reset and read is presented for the first time to our knowledge. An innovative reading strategy is proposed. The selector switching is performed only if the RRAM cell is in the Low Resistive State (LRS), while the reading of the High Resistive State (HRS) is performed without switching the OTS selector, preventing disruptive reading when the RRAM cell is in HRS. Up to 106 read cycles have been demonstrated with a stable memory window of one decade and a stable OTS OFF state.

International audience; While perpendicular STT-MRAM are seen as a promising next-generation memory, retention becomes critical and must be characterized precisely. Four extraction methods are explained taking special emphasize on accuracy and precision. They are then applied from single cell to kb-array, from 50 to 250 nm diameter cells and up to 235°C in order to show the limitations and advantages of each method.

Conference of 62nd IEEE International Electron Devices Meeting, IEDM 2016 ; Conference Date: 3 December 2016 Through 7 December 2016; Conference Code:126284; International audience; In this paper, we propose a new circuit architecture and a reading/programming strategy to emulate both Short and Long Term Plasticity (STP, LTP) rules using non-volatile OxRAM cells. For the first time, we show how the intrinsic OxRAM device switching probability at ultra-low power can be exploited to implement STP as well as LTP learning rules. Moreover, we demonstrate the computational power that STP can provide for reliable signal detection in highly noisy input data. A Fully Connected Neural Network incorporating STP and LTP learning rules is used to demonstrate two applications: (i) visual pattern extraction and (ii) decoding of neural signals. A high accuracy is obtained even in presence of significant background noise in the input data.

While Resistive RAM (RRAM) are seen as an alternative to NAND Flash, their variability and cycling understanding remain a major roadblock. Extensive characterizations of multi-kbits RRAM arrays during Forming, Set, Reset and cycling operations are presented allowing the quantification of the intrinsic variability factors. As a result, the fundamental variability limits of filament-based RRAM in the full resistance range are identified.

An alternative solution to standard Flash memories is represented by nitride-trap memories as silicon–oxide–nitride–oxide–silicon (SONOS) or nitrided read only memory (NROM) memories. However these structures are facing retention issues at high temperature and a quantitative analysis of the location of the charge during program and retention is required. This work investigates the location of charge of NROM Nonvolatile memory devices in order to evaluate the trapped charge distribution in program and retention conditions for Si3N4, Al2O3, and HfO2 trapping layers. During programming, the charge is initially injected on a 40–60-nm-length region in the trapping layer, then after reaching a trapped charge saturation level, it broadens. The charge saturation level is explained through electrostatic considerations and not by a limit of available number of traps. During retention, the lateral migration (inside the trapping layer) and vertical migration (charge loss) of the trapped charge are quantitatively evaluated. Thanks to a one-dimensional (1D) drift model, the characterization of lateral migration at room temperature is put in relation to the trap properties of Si3N4, Al2O3, and HfO2 layers.

International audience

In this paper, we present a semi-analytical model tailored for nitride Charge-Trap TriGate (CT-3G) non-volatile memories under uniform stress: Fowler-Nordheim (FN) program (P) and erase (E) performances are reproduced. This model presents innovations in the tunnelling current calculation at corners through the Hankel function formalism. The validation of the model is operated through extensive comparisons with experimental data obtained on ultra-scaled devices with different aspect ratios and gate stacks. Scaling opportunities of such kind of 3D devices are deeply discussed.

Here we present a semi-analytical model for nanocrystal-based (NCs) FinFLASH memories under uniform stress: Fowler-Nordheim (FN) write/erase, gate disturb and data retention are addressed. This model is able to catch the essential features related to the non-uniform trapped charge distribution in such a complex 3D structure. Both body tied and SOI devices are included in the model. Main conclusions are related to the different characteristic times of charge trapping over fin corners or planar fin regions: double dynamics during programming, intrinsic disturb immunity of written state in FF cells. The aspect ratio impact on DeltaVTH is also evaluated showing a slightly better performance of body tied devices.

OxRAM technology is one of the strongest candidates for embedded solutions at scaled nodes (

We demonstrate, for the first time, 3D monolithically integrated multiple 1T1R Resistive RAM (RRAM) structure storing up to 3.17 bits per RRAM. We study, using a 4 kb 1T1R array, the impact of the conductance relaxation after Multi-Level Cell (MLC) programming. We show that traditional storage applications may be limited to 2 bits per RRAM due to the overlap between conductance ranges after relaxation. On the other hand, our study concludes that conductance relaxation effect is negligible for Neural Network (NN), allowing the use of nine distinct conductance levels per RRAM (equivalent to 3.17 bits) with minimal inference accuracy loss.

This paper explores a novel 3D one transistor / one RRAM (1T1R) memory cube. The proposed architecture integrates HfO 2 -based OxRAM with select junctionless (JL) transistors based on low-voltage Gate-All-Around (GAA) stacked NanoSheet (NS) technology. A bitcell size of 23.9×F2/N is achieved (‘N’ being the number of stacked-NS) as well as a very high write and read parallelism. Extensive characterization of JL transistors and OxRAMs is performed to show their ability to be co-integrated inside a same 1T1R memory cell. Electrical characterization of 4kbits OxRAM arrays shows a large memory window (HRS/LRS=20) up to 104 cycles with a current compliance of 150µA, compatible with the performances of our JL transistors. Then, we experimentally demonstrate scouting logic operations capability with 2 operands, which should be extended to 4 operands thanks to an original two cells/bit “double coding” scheme assessed by SPICE simulations. Finally, we evidenced that this computing scheme is 2 times more energy efficient than a write-verify approach.

International audience; In this paper we compare the performances of SiN with respect to an optimized SiC encapsulation in Wall based Phase-Change Memory (PCM) integrating a Ge-rich Ge-Sb-Te alloy (GGST) suitable for high temperature stability in automotive applications. Thanks to the electrical characterization of 4kb arrays, 3D electro-thermal simulations and TEM analyses performed on programmed devices, we demonstrate the higher programming efficiency in SiC-based PCM devices, thanks to the lower thermal conductivity of the optimized encapsulation. Indeed, the uniform temperature profile achieved in the active layer of SiC encapsulated PCM leads to a retention of one hour at 250°C. A theoretical model is here proposed to describe the electro-thermal behavior of the device, linking the electrical properties, such as the resistance as a function of current characteristics, to the thermal conductivity of the materials that constitute the device. Finally, thanks to our findings, we provide some guidelines to achieve drastic current reduction via the thermal engineering of the next generation PCM technology.