Search

The rationale and development of a wafer-scale three-dimensional (3-D) integrated circuit technology are described. The three-dimensional intergration process is described as well as the properties of the four enabling technologies.

Studies the defect-related dielectric breakdown, charge trapping and interface-state generation of gate oxides on zone-melting-recrystallized (ZMR) silicon-on-insulator films. Identification of the weak spots for the breakdown of gate oxides; Correlation of the weak spots with the defects in the ZMR films; Breakdown histograms for metal oxide semiconductor capacitors on a bulk silicon wafer and ZMR films.

Single event transients are characterized for the first time in logic gate circuits fabricated in a novel 3DIC technology where SET test circuits are vertically integrated on three tiers in a 20-\mu\ m-thick layer. This 3D technology is extremely well suited for high-density circuit integration because of the small dimension the tier-to-tier circuit interconnects, which are 1.25-\mu\ m-wide through-oxide-vias. Transient pulse width distributions were characterized simultaneously on each tier during exposure to krypton heavy ions. The difference in SET pulse width and cross-section among the three tiers is discussed. Experimental test results are explained by considering the electrical characteristics of the FETs on the 2D wafers before 3D integration, and by considering the energy deposited by the Kr ions passing through the various material layers of the 3DIC stack. We also show that the back metal layer available on the upper tiers can be used to tune independently the nFET and pFET current drive, and change the SET pulse width and cross-section. This 3DIC technology appears to be a good candidate for space applications. [ABSTRACT FROM PUBLISHER]

Radiation effects are presented for the first time for vertically integrated 3 \times 64-kb SOI SRAM circuits fabricated using the 3D process developed at MIT Lincoln Laboratory. Three fully-fabricated 2D circuit wafers are stacked using standard CMOS fabrication techniques including thin-film planarization, layer alignment and oxide bonding. Micron-scale dense 3D vias are fabricated to interconnect circuits between tiers. Ionizing dose and single event effects are discussed for proton irradiation with energies between 4.8 and 500 MeV. Results are compared with 14-MeV neutron irradiation. Single event upset cross section, tier-to-tier and angular effects are discussed. The interaction of 500-MeV protons with tungsten interconnects is investigated using Monte-Carlo simulations. Results show no tier-to-tier effects and comparable radiation effects on 2D and 3D SRAMs. 3DIC technology should be a good candidate for fabricating circuits for space applications. [ABSTRACT FROM PUBLISHER]