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The effective work function (WF) of Ni3Si2 was evaluated on HfSixOy and SiO2 dielectrics. Ni3Si2 forms, in thin film Ni–Si diffusion couples with Ni to Si composition ratios between 1 and 2, after formation of a Ni2Si/NiSi stack and by its reaction at moderate thermal budgets (comparable to those used in back end processing of complementary metal-oxide-semiconductor circuits). Ni3Si2 formation limits, on the Ni-rich side, the process window for NiSi fully silicided (FUSI) gates (NiSi at interface with dielectric) to reacted Ni–Si ratios <1.5. The WF of Ni3Si2 was found to have similar values and behavior to that of NiSi, both on SiO2 (showing similar modulation with dopants) and on HfSixOy, in contrast to Ni-richer silicides such as Ni2Si and Ni31Si12 which do not exhibit significant WF modulation with dopants on SiO2 and have considerably higher WF on HfSixOy. This suggests that the chemistry and structure of the original NiSi/dielectric interface are not modified significantly by the subsequent growth of Ni3Si2 and implies that its formation may be tolerable when targeting NiSi FUSI gates, thereby expanding the process window for this application. [ABSTRACT FROM AUTHOR]

The CMOS integration of dual work function (WF) phase-controlled Ni fully silicided (FUSI) gates on HfSiON was investigated. For the first time, the integration of NiSi FUSI gates on n-channel MOS (NMOS) and Ni31Si12 FUSI gates on p-channel MOS (PMOS) with good Vt control to short gate lengths (LG = 50 nm, linear Vt of 0.49 V for NMOS, and -0.37 V for PMOS) is demonstrated. A poly-Si etch-back step was used to reduce the poly-Si height on PMOS devices, allowing for the linewidth-independent formation of NISi on NMOS and Ni-rich silicides on PMOS with a two-step rapid thermal processing (RTP) silicidation process. The process space for the scalable formation of NiSi on NMOS and Ni2Si or Ni31Si12 on PMOS devices was investigated. It was found that within the process window for linewidth-independent NiSi FUSI formation on 100-nm poly-Si NMOS devices, it is possible to control the silicide formation on PMOS devices by adjusting the poly-Si etch-back and RTP1 conditions to obtain either Ni2Si or Ni31Si12 FUSI gates. A reduction in the PMOS threshold voltage of 90 mV and improved device performance (18% Ion improvement at Ioff = 100 nA/µm) was obtained for Ni31Si12 compared to Ni2Si FUSI gates, as well as a Vt reduction of 350 mV when compared to a single WF flow using NiSi FUSI gates on PMOS. [ABSTRACT FROM AUTHOR]