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This article presents analysis, design details, and measurement result of a 224-Gb/s four-level pulse amplitude modulation (PAM-4) transmitter (TX) consisting of a 7-bit voltage digital-to-analog converter (DAC) driver, digital 8-tap feed-forward equalizer (FFE), and a 28-GHz inductively peaked clock distribution network. The TX DAC uses quarter-rate clocking with a 4:1 pulse-based data serialization architecture. Design techniques for generating and distributing low-jitter CMOS clocks up to 29 GHz, timing closure in the serializer, 112-Gbaud 4:1 data MUX using 1-UI pulse generator, and bandwidth/return loss/group delay optimized output pad network using a 9th-order LC filter are described. Fabricated in the Intel 10-nm FinFET process technology, the TX demonstrates random jitter (RJ) of 65 fsrms with nominal output swing of $1.0~V_{\mathrm {ppd}}$ at 224 Gb/s achieving 1.88-pJ/b energy efficiency including an on-die LC phase-locked loop (PLL). To the best of authors’ knowledge, this TX achieved the highest data rate with the lowest RJ for CMOS SerDes TXs reported to date. [ABSTRACT FROM AUTHOR]

A triple-mode class-AB balanced linear power amplifier (PA) is realized in standard 0.18-\mu\ m CMOS technology. For the average efficiency enhancement, the triple-mode operation realizes a switched-quadrature coupler with a balanced topology to achieve robust load insensitivity. The PA and RF switches uniquely utilize the isolation port of the switched-quadrature coupler as a signal path in a low-power (LP) mode of operation, and the incorporated output matching network satisfies the \vert\Gamma\vert=1 condition from the quadrature coupler in the LP mode while providing the necessary load-pull impedance from the PA output side in the high-power (HP) mode. To obtain low loss and high quality factor (Q) of the passive output-combining network, a transformer-based quadrature coupler is implemented using a silicon-based integrated passive device process. With a 3.4-V power supply, the PA transmits a maximum output power of 28.4 dBm with 40.7% of power-added efficiency (PAE) and linear output power up to 26.6 dBm with 35% of the PAE using a 3-GPP WCDMA modulated signal. With the triple-mode operation, a PAE at 16 dBm is enhanced from 11.1% to 17%, and 47 mA of quiescent current is saved. The PA also shows robust operation under 2.5:1 of VSWR condition, achieving 1 dB of the gain variation and less than 3.9 dB of ACLR variation. This work demonstrates the potential of a highly efficient CMOS PA for WCDMA applications. [ABSTRACT FROM AUTHOR]

In this paper, a linear CMOS power amplifier (PA) with high output power (34-dBm saturated output power) for high data-rate mobile applications is introduced. The PA incorporates a parallel combination of four differential PA cores to generate high output power with good efficiency and linearity. To implement an efficient on-chip power combiner in a small form-factor, we propose a parallel-series combining transformer (PSCT), which mitigates drawbacks and limitations of conventional power-combining transformers such as a series combining transformer (SCT) and a parallel combining transformer (PCT). Using the proposed PSCT, a two-stage class-AB PA is designed and fabricated in a 0.18-\mu\m CMOS technology. The PA achieves a P 1∼dB of 31.5 dBm , a P sat of 34 dBm, and a P linear of 23.5 dBm with a peak PAE of 34.9% (peak drain efficiency of 41%) at the operating frequency of 2.4 GHz . A detailed analysis of the proposed PSCT is introduced along with comparisons to the conventional monolithic power-combining transformers. A design methodology of the integrated CMOS PA is also presented. [ABSTRACT FROM AUTHOR]

A dual-mode CMOS power amplifier (PA) with an integrated tunable matching network is presented. A switched capacitor is fully analyzed to implement a tunable matching network in terms of power-handling capability, tuning ratio, quality factor, and linearity. Based on the presented consideration, a 3.3-V 2.4-GHz fully integrated CMOS dual-mode PA is implemented in a 0.18-\mum CMOS process. The PA has two power modes, high-power and low-power (LP), and each mode is optimally matched by the tunable matching network. The LP mode enables more than 50% dc current reduction from 0- to 10-dBm power range. The improved efficiency in this study is approximately twice that of other multimode CMOS PAs reported thus far. [ABSTRACT FROM PUBLISHER]

Efficiency degradation effects of power combining transformers with partially disabled inputs are quantitatively analyzed. To improve efficiencies in lower-power modes of a multi-mode class-AB power amplifier (PA), a discrete resizing technique is introduced in combination with a parallel-combining transformer (PCT). The two-stage PA implemented in a 0.18-\mu\m CMOS technology also includes varactor-based tunable matching circuits. The design method involves parallel-combining of two power stages, each of which are divided into three sub-cells to facilitate discrete resizing. The parallel-combining of concurrently resized power cells minimizes undesired power loss through the transformer and helps the PA to utilize the transformer efficiency maximally independent of the number of combining cells. When operating in the high-power mode, the PA exhibits a peak output power of 31 dBm with a PAE of 34.8%. Power back-offs are realized by discretely turning off parallel sub-amplifier cells concurrently, achieving output power levels of 26 dBm and 22.3 dBm with respective PAE of 22.5% and 15%. The EVM has been measured with IEEE 802.11g WLAN and 802.16e WiMAX modulated signals in three operation modes. In the high-power mode, the PA dissipates 590 mA from a 3.3 V supply. [ABSTRACT FROM PUBLISHER]