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With continuously decreasing circuit scale, more and more test patterns (test contents) are added to test set to achieve acceptable defect levels, which seriously affect test time and, consequently, test cost. Theoretically, dropping invalid (pattern that can make the test pass) test patterns can reduce test cost. In fact, When the valid (pattern that can make the test fail) and invalid patterns overlap seriously, identifying effective patterns performs poorly, which will not achieve the expected results. This paper proposes a kind of eliminate redundancy method, so that this LDA-MRMR algorithm which can provide test cost reduction without increasing the defect level obviously. Experimental results demonstrate that the proposed method sacrifices 3% of the predictive accuracy in exchange for 3.7 times time saving compared with traditional methods. In addition, the algorithm is completely software-based and does not require any additional hardware overhead and is directly compatible with traditional integrated circuit testing process. • This paper provides test cost reduction without increasing the defect level obviously. • We find the optimal solution between test cost and test quality. • Mathematical model was proposed to make it is possessed of stronger applicability and generality. • Test time and test quality have been greatly improved. [ABSTRACT FROM AUTHOR]

• Improvement by cascade cycles for energy harvesting of solid oxide fuel cell. • New cascade system based on supercritical carbon dioxide cycle. • Analyses in terms of energy, exergy and economic performance. • Investigate three key parameters' impacts on systemic performance. Solid oxide fuel cell has become one of the most promising power generation methods today due to its diverse fuel sources, high efficiency, easy maintenance, and environmental friendliness. However, the exhaust gas temperature of the solid oxide fuel cell is still too high, and its direct emissions will cause a large amount of energy loss. To further improve the efficiency of the SOFC/GT system, a novel cascade waste heat recovery system is designed where the top cycle is the Brayton supercritical carbon dioxide cycle and the bottom cycle is the organic Rankine cycle. In order to better evaluate the performance of the system, this paper first carried out thermodynamic analysis of the subsystem respectively, and obtained the exergy flow process of the system. Then, an economic model is established for the entire system and calculated the annual total cost rate. The results are: the system efficiency can reach 73.97%, and the corresponding total cost rate of system operation is 36.25 $/MWh, reflecting excellent performance. [ABSTRACT FROM AUTHOR]

The improvement in energy efficiency of the waste-to-energy plant (WTE) is limited due to the heat loss of flue gas and bottom ash. Many scholars have conducted the optimization studies on waste heat recovery system in WTE plant from the perspective of determining optimal system working parameters. However, few researchers pay attentions to reducing the cost of the system by cutting down the number of system components while guaranteeing the system performance. In this study, a novel waste heat recovery system combining a transcritical CO 2 system, an organic Rankine cycle (ORC), and a compression heat pump/refrigeration system is proposed. The compression heat pump system can be converted into a compression refrigeration system without replacing any equipment, which is beneficial to reducing the cost of the system. Comprehensive thermodynamic, economic, and environmental analyses are performed to examine the performance of the system. Multi-objective optimization (NSGA-II) is utilized to obtain the optimal working parameters in both district heating and space cooling modes. Results indicate that the maximum energy and exergy efficiencies of the WTE coupled with waste heat recovery system are 71.75% and 67.92%, respectively. The value of ecological efficiency and dynamic payback period are 94.05% and 4.33 years, respectively. The maximum pressure of transcritical CO 2 has positive effects on transcritical CO 2 cycle while it has negative effects on the whole waste heat recovery system. The increment in evaporator pressure of ORC leads to a decrement in energy efficiency in district heating mode, but it improves the economic performance in space cooling mode. The optimal working parameters of both district heating and space cooling modes are determined. The maximum net present value (NPV) and minimum cost of the system are 20.40 M$ and 2.44 M$, respectively. The cost of the system descends greatly while the NPV slightly decreases. The comprehensive and sufficient theoretical analysis reveals the huge potential of waste heat recovery in WTE plant and provides a strategy to reduce the energy consumption as well as improving the economic and environmental performance. • A novel cascade waste heat recovery system in waste-to-energy plant was proposed. • Thermodynamic analysis and environmental analysis were carried out. • The economic performance was obtained by net present value (NPV). • Multi-objective optimization results showed that the maximum NPV reached 20.4 M$. • The maximum energy and exergy efficiencies were 71.75% and 67.92%, respectively. [ABSTRACT FROM AUTHOR]

This paper presents a novel radiation hardened latch (namely DCTELC) that can completely tolerate single-node upsets and double-node upsets (DNUs) for high-performance applications. The latch mainly consists of a clock-gating based dual-interlocked-cell (DICE), a 2-input C-element, and a clock-gating based 2-input C-element. The latch introduces isolated nodes to tolerate DNUs and the isolated nodes have no time to float for high-performance applications. Simulation results demonstrate the complete DNU tolerance for the latch and an 86% power-area-delay product (PADP) saving on average compared with state-of-the-art DNU-tolerant latches. Moreover, compared with the existing latches of the same type, the power dissipation, silicon area, transmission delay, and PADP of the proposed latch are the smallest. • A double-node-upset completely tolerant CMOS latch design is proposed. • The latch has extremely low cost compared with the same type latches. • The latch is suitable for high-performance applications due to low delay. [ABSTRACT FROM AUTHOR]

—To address the issue of maladaptive reliability theory models in delay-based physical unclonable functions (PUF) of ring classes, this paper begins by analyzing the relationship between four key transistor parameters (channel length, channel width, threshold voltage, and gate oxide thickness) and delay sensitivity. Then establishes reliability quantification formulas for various PUF types, including ring oscillator PUF, k-out-of-1 PUF, Loop PUF, transient effect ring oscillator PUF, and duty cycle PUF. This analysis and comparison are conducted using the inverter delay model and probabilistic statistical methods to ensure fairness at the theoretical level. Finally, the proposed model is validated through simulation experiments, along with further analysis and comparison of ring-PUF. The results demonstrate that delay sensitivity can be utilized to assess the extent of delay impact when process parameters fluctuate. In terms of reliability, the ring-PUF can be ranked as follows: k-out-of-1 PUF, Loop PUF, ring oscillator PUF, transient effect ring oscillator PUF, and duty cycle PUF. This paper offers extensive technical guidance and theoretical support for ring PUF designers. [ABSTRACT FROM AUTHOR]

Single event upset (SEU) threatens the reliability of spaceborne integrated circuits (ICs). As the process of transistors continues to scale, Single-Node-Upset (SNU) and Double-Node-Upset (DNU) hardened circuits no longer meet the requirements of high reliability. A disadvantage of previous Triple-Node-Upset (TNU) hardened circuits is high overhead. Therefore, this paper proposes a fault-avoidance TNU-resilient latch (FATNU) using approximate C-elements (ACs) and new fault-avoidance C-elements (FACs). Simulation results demonstrate that FATNU achieves TNU resilience with low overhead compared with reference latches due to the use of the clock-gating technique and cross-feedback loop. In particular, compared with previous TNU-resilient latches, the FATNU latch is the best in delay, power, and area overhead. Moreover, the proposed FATNU latch is insensitive to process, voltage, and temperature (PVT) variations. [ABSTRACT FROM AUTHOR]

This paper presents an Interconnection heterogeneous and High-speed Triple-node-upset Recovery Latch (IHTRL). This latch utilizes homogeneous elements to construct a 4 × 4 array in four levels. The point is heterogeneous interconnection of each level. Compared with the traditional interconnection way, the proposed heterogeneous interconnection can block the propagation of TNU effectively. The IHTRL can effectively realize TNU recovery by the blocking ability of C-elements and heterogeneous interconnection. The IHTRL utilizes the high-speed path and clock-gating technique to reduce performance penalty and power consumption. Compared with TNU recovery latches LCTNURL and TNURL, the proposed IHTRL is the best in terms of delay, area overhead and PDP. Compared with TNU tolerant and recovery latches, the IHTRL achieves 81.96% reduction in delay on average, 85.91% reduction in PDP on average and 85.46% reduction in APDP on average, at the cost of 7.14% increase in power consumption and 13.21% increase in area overhead on average. Analysis shows that the IHTRL is insensitive to PVT variations. [ABSTRACT FROM AUTHOR]

With the continuous scaling of CMOS feature sizes, single event triple-node-upset (TNU) induced by charge sharing has become a serious reliability issue. This paper presents a low-cost triple-node-upset self-recovery latch (LC-TSL) which is composed of N-elements, P-elements and C-elements. The LC-TSL utilizes a two-dimensional feedback array composed of four rows and four columns to achieve triple-node-upset recovery. It utilizes high-speed transmission path to achieve high performance and clock-gating to reduce power consumption. The extensive simulation results show that the LC-TSL achieves high speed, low power consumption and 100% TNU recovery. Compared with the average of previous eight hardened latches, the LC-TSL reduces the delay by 78.59% and reduces the power-delay-product by 79.69%, while only increases 15.15% area overhead and 15.38% power consumption overhead. Compared with TNU self-recoverable latches, the LC-TSL is the best in terms of area, delay, and PDP. The LC-TSL achieves TNU-recovery ability and low cost overhead, and it is insensitive to voltage and temperature variations. [ABSTRACT FROM AUTHOR]

With the continuous scaling of feature sizes, latches are becoming more and more sensitive to the multiple-node upsets (MNUs) induced by radiation. Based on input-split C-elements and a redundant feedback scheme, we propose a triple-node-upset-resilient latch (ISC-TRL) and a quadruple-node-upset-resilient latch (ISC-QRL) to provide high reliability. Using the novel interconnection scheme between the four-level input-split C-elements, any possible triple-node upset (TNU) or quadruple-node upset (QNU) occurred in the proposed latches can be filtered level by level, respectively. HSPICE simulation performed in 14 nm FinFET technology show that, compared with relevant MNU-hardened latches, the proposed ISC-TRL latch can reduce the delay-power-area product (DPAP) by 89.81% and only introduces 3.85% area overhead on average, while achieving 100% TNU-resilience and 99% QNU-resilience. The proposed ISC-QRL latch can reduce the DPAP by 83.01% and introduce 38.46% area overhead on average, while achieving 100% QNU-resilience. In addition, Monte Carlo simulation results show that the proposed ISC-TRL and ISC-QRL latches are of low sensitivity to process, voltage and temperature (PVT) variations. [ABSTRACT FROM AUTHOR]

With the continuous scaling of IC technology, latches becomes more vulnerable to double-node-upset (DNU) and triple-node-upset (TNU). The node separated (NS) method applied for DNU hardening has not been used for TNU hardening to effectively reduce the probability of TNU occurrence, resulting in excessive power consumption, delay and area overhead of TNU hardening. This paper proposes a low-overhead TNU self-recoverable latch, named Node Separated Triple-node-upset Self-recoverable Latch (NS-TSL). NS-TSL includes four N-type stacked structures, four P-type stacked structures, a clock gating based inverter, and a high-speed transmission path. Based on a physical flip mechanism that makes sensitive nodes flip in one direction and multiple feedback mechanism, NS-TSL can realize TNU self-recovery. Simulation results demonstrate that compared with the other six TNU hardened latches, NS-TSL reduces the delay by 62.24%, the power consumption by 59.96%, the power delay product by 84.04%, and the area by 27.97% on average. Moreover, NS-TSL is insusceptible to temperature and voltage variations. [ABSTRACT FROM AUTHOR]

This paper presents a dual-modular-redundancy and dual-level error-interception based triple-node-upset (TNU) tolerant latch design (namely DDETT) for safety-critical applications. The DDETT latch comprises two parallel single-node-upset self-recoverable cells to store values and three C-elements to intercept errors. Both of the two cells are constructed from triple mutually-feeding-back 2-input C-elements, and the cells feed two internal C-elements for first-level error-interception. Moreover, the two internal C-elements feed an output-stage C-element for second-level error-interception, making the DDETT latch TNU-tolerant in that it can tolerate any possible TNU. This paper further presents a low-cost version of the DDETT latch, namely LCDDETT. The LCDDETT latch uses two dual-interlocked-storage-cells (DICEs) to store values and uses dual-level error-interception to tolerate any possible TNU with cost-effectiveness. Simulation results not only confirm the TNU-tolerance of the proposed latches but also demonstrate that the delay-power-area products of the DDETT and LCDDETT latches are reduced by approximately 34% and 58%, respectively. [ABSTRACT FROM AUTHOR]