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In this paper, for the first time, we present a detailed RF experimental and simulation study of a 3-D multichannel SOI MOSFET (MCFET). Being different from the conventional planar technology, the MCFET features a total of three self-aligned TiN/HfO2 gate stacks fabricated on top of each other, allowing current to flow through the three undoped ultrathinned bodies (UTBs). In other words, the operation of the MCFET theoretically based on two UTB double-gate SOIs and a single-gate UTB fully depleted SOI (FDSOI) at the bottom. Using on-wafer S-parameters, the RF/analog figures-of-merit of an MCFET a gate length of 50 nm are extracted and discussed. Thanks enormous transconductance (gm) and very low output conductance, the RF/analog performances of MCFET-voltage gain (AVI) and early voltage (VEA) are superior compared with that single-gate UTB-FDSOI. However, these advantages diminish in terms of transition frequency (fT), due to the large total input gate capacitances (CGG). This inspires the introduction of spacer engineering in MCFET, aiming at improving both CGG and fT. The sensitivity of the spacer length to the RF/analog performances is experimentally analyzed, and the performance optimization is validated using ac simulation. This paper concludes that optimized MCFETs are a serious contender to the mainstream MOSFETs including FinFETs for realizing future low-power analog applications. [ABSTRACT FROM AUTHOR]

In this paper, measured RF noise performance of graded-channel metal-oxide-semiconductor (MOS) transistors (GCMOS--also named laterally asymmetric channel transistors) shows impressive reduction in minimum noise figure (N Fmin) as compared to classical MOSFET transistors (with the same gate length Lg = 0.5 μm). The reason is proven to be because of the higher noise correlation coefficient (C). GCMOS also shows lower sensitivity to extrinsic thermal noise as compared to classical MOSFET. Moreover, it is demonstrated that the use of 0.5-μm-gate-length GCMOS gives a competitive RF noise performance as compared to 0.25-μm-gate-length classical nMOS transistors. [ABSTRACT FROM AUTHOR]

Abstract: For the first time, the high frequency (HF) performance of an ultra-thinned body (UTB) fully depleted silicon-on-insulator (FDSOI) incorporating TiN/HfO2 gate stack is reported. Full small signal equivalent parameters of UTB-FDSOI are extracted and analysed in detailed. It is revealed that UTB-FDSOI with longer unit width WU (same total width WTOT ) results in slightly higher gm that leads to better HF performance. Despite of the mobility degradation due to the quality of the interface between the high-K dielectric and silicon, the measured transition frequency (fT ) still corresponds well to that predicted from the ITRS roadmap. Optimising the gate stack for low RG is crucial as huge RG in the current technology is the key parameter responsible for the low fMAX obtained. This work can also be considered as the first ever experimental device measured suitable to be used for the Low STand-by Power (LSTP)-based RF/mobile application. [Copyright &y& Elsevier]

For the first time, internal spacers have been introduced in multichannel CMOSFET (MCFET) structures, featuring a decrease of the intrinsic CV/I delay by 39%. The process steps introduced for this new MCFET technological option are studied and optimized in order to achieve excellent ION/IOFF characteristics (NMOS: 2.33 mA/μm at 27 pA/μm and PMOS: 1.52 mA/μm at 38 pA/μm). A gate capacitance Cgg reduction of 32% is measured, thanks to S-parameter extraction. Moreover, a significant improvement of the analogical figure of merit is measured compared with optimized fully depleted silicon-on-insulator planar reference; the voltage gain AVI (= gm /gds) is improved by 92%. [ABSTRACT FROM AUTHOR]

This paper presents a detailed RF study for source/drain Schottky-barrier (SB) MOSFETs. Using on-wafer S-parameters, high-frequency (HF) figures-of-merit (FoMs) and small-signal equivalent circuits (SSEC) are first extracted and discussed for a 120-nm-gate-length SB MOSFET. Then, using ac simulations, HF FoM's sensitivity along SB height and underlap length variations are subsequently presented. The whole study provides, for SB MOSFETs, a deep understanding of key ac-element (transconductances and capacitances) behavior as well as process-parameter optimization to achieve the best HF FoMs. [ABSTRACT FROM AUTHOR]