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This article presents analysis, design details, and measurement result of a 224-Gb/s four-level pulse amplitude modulation (PAM-4) transmitter (TX) consisting of a 7-bit voltage digital-to-analog converter (DAC) driver, digital 8-tap feed-forward equalizer (FFE), and a 28-GHz inductively peaked clock distribution network. The TX DAC uses quarter-rate clocking with a 4:1 pulse-based data serialization architecture. Design techniques for generating and distributing low-jitter CMOS clocks up to 29 GHz, timing closure in the serializer, 112-Gbaud 4:1 data MUX using 1-UI pulse generator, and bandwidth/return loss/group delay optimized output pad network using a 9th-order LC filter are described. Fabricated in the Intel 10-nm FinFET process technology, the TX demonstrates random jitter (RJ) of 65 fsrms with nominal output swing of $1.0~V_{\mathrm {ppd}}$ at 224 Gb/s achieving 1.88-pJ/b energy efficiency including an on-die LC phase-locked loop (PLL). To the best of authors’ knowledge, this TX achieved the highest data rate with the lowest RJ for CMOS SerDes TXs reported to date. [ABSTRACT FROM AUTHOR]

This paper presents a low power bio-signal acquisition system for sleep apnea, which can measure respiration, heart rate, SpO2, and pulse transit time (PTT). For respiration, a nasal airflow sensor with a thermistor is used. For PTT that can serve as a surrogate for blood pressure during sleep, two photoplethysmogram (PPG) sensors are employed at the upper arm and the finger. For improved comfort during sleep, body channel communication (BCC) is used to remove long wires. To reduce power consumption and circuit complexity, sensor’s analog front-end is implemented by using a current-controlled oscillator which is also shared by BCC transmitter that employs analog frequency modulation. Implemented in $0.18~\mu \text{m}$ CMOS, the proposed IC consumes less than 3.6 mW from a 1.8 V supply, while occupying 0.145 mm2 of active area. [ABSTRACT FROM AUTHOR]

Modern wireless systems are evolving toward a heterogeneous environment where multiple radio access technologies (RATs) coexist. Most of the RATs in current use operate independently of each other, however, there is an increasing demand for coordination among different RATs in order to support exponentially growing wireless traffic. Our goal in this paper is to design a super-MAC that integrates multiple RATs in a tightly coupled manner. To this end, we propose an architecture for super-MAC, and develop an algorithm that splits IP traffic into multiple RATs and controls each RAT to exploit multi-RAT diversity. We prove the asymptotic optimality of the super-MAC algorithm by introducing a novel reference system that enables the analysis of the multi-RAT system where there is a mixture of slotted (such as cellular) and unslotted (such as WiFi) RATs. Through extensive simulations we show that the super-MAC algorithm can enhance the quality of service including throughput, energy efficiency, and fairness. [ABSTRACT FROM AUTHOR]

A fundamental question in the study of location-based mobile sensing is how much energy can be saved while still guaranteeing the reliable localization accuracy. In this paper, we analyze key features of human proximity and find a motivation which implies that the energy-efficient and accurate localization is possible by sharing the locations of nearby mobile devices. From the location-based collaborative sensing idea, we formulate an optimization problem which aims to minimize the total number of location measurements for a given fairness criterion. Then, we propose a practical and distributed location sharing (DLS) protocol and an optimal parameter control algorithm (OWD) which makes the DLS protocol attain an asymptotic optimal performance. Via extensive simulations under various environments including real mobility traces, we verify that the proposed DLS+OWD policy significantly reduces the average power consumption of mobile devices with a higher fairness compared to the existing algorithms. [ABSTRACT FROM AUTHOR]

This paper presents a reconfigurable 56 GS/s transmitter (TX) that operates up to 112 Gb/s with four-level pulse-amplitude modulation (PAM-4) and at 56 Gb/s with non-return-to-zero (NRZ) modulation scheme. Fabricated in the 10-nm FinFET technology, the TX incorporates a four-way interleaved quarter-rate architecture with a three-tap feed-forward equalizer (FFE). Key features of the TX include a 1-UI pulse-generator-based 4:1 serializer combined with a current-mode logic (CML) driver, low-power data-serializing paths, an output pad-network using a multi-segment $\pi $ -coil for bandwidth co-optimization together with ESD diodes, sub-80-fs resolution duty-cycle detector/corrector (DCD/DCC) and quadrature-error detector/corrector (QED/QEC) circuits, and a hybrid LC-phase-locked loop (PLL) with quadrature clock distribution circuits. The TX operating at 112 Gb/s in PAM-4 modulation consumes 232 mW from 1- and 1.5-V supplies, achieving an 2.07 pJ/b energy efficiency. The TX front end occupies an area of 0.0302 mm2. [ABSTRACT FROM AUTHOR]

We consider energy efficient base station (BS) sleeping and clustering problems in cooperative cellular networks, where clusters of base stations jointly transmit to users. Our key idea of energy saving is to exploit spatio-temporal fluctuation of traffic demand, and use minimal energy to provide achievable data rate only slightly greater than varying traffic demand. However, it is highly challenging to design traffic-aware algorithms without the future traffic demand information. To overcome this difficulty, we develop joint BS sleeping and clustering algorithms using queue instead of the future traffic information. The queue length information captures spatio-temporal mismatch between traffic demand and offered data rate. For BS clustering problem, we propose an optimal algorithm under given BS sleep mode state that has polynomial complexity. We integrate the optimal clustering solution into the sleeping problem, which is a complex combinatorial problem, and develop a joint optimal clustering and sleeping algorithm with reduced complexity compared to the exhaustive search. We also develop a greedy algorithm that finds a near-optimal clustering and sleeping solution with polynomial complexity. Through extensive simulations, we show that the proposed algorithms can save significant energy when traffic load is low. [ABSTRACT FROM PUBLISHER]

We consider the problem of providing inter-access-point (AP) fairness guarantee in dense AP deployments where starvation can occur. In particular, we develop a framework for providing robust minimum throughput guarantee for each AP under the uncertainty of user distributions. Our framework consists of an AP throughput provisioning scheme and a distributed CSMA algorithm. The throughput provisioning scheme computes a robust feasible minimum AP throughput vector based on a random AP-level conflict graph and chance-constrained optimization. By incorporating the minimum throughput vector, we develop a distributed CSMA algorithm that fulfills the minimum requirement for each AP and is compatible with the IEEE 802.11 standard. We show through extensive simulations that our framework addresses the AP starvation problem by guaranteeing minimum throughput for each AP. [ABSTRACT FROM PUBLISHER]

We present a wide-angle, nonmechanical laser beam steerer based on polymer polarization gratings with an optimal design approach for maximizing field-of-regard (F\!O\!R ). The steering design offers exponential scaling of the number of steering angles, called suprabinary steering. The design approach can be easily adapted for any 1-D or 2-D (e.g., symmetric or asymmetric FOR) beam steering. We simulate a system using a finite difference and ray tracing tools and fabricate coarse beam steerer with 65^{\circ} F\!O\!R with \sim 8^{\circ} resolution at 1550 nm. We demonstrate high optical throughput (84\%$ –87$\%$) that can be substantially improved by optimizing substrates and electrode materials. This beam steerer can achieve very low sidelobes and supports comparatively large beam diameters paired with a very thin assembly and low beam walk-off. We also demonstrate using a certain type of LC variable retarder that the total switching time from any steering angle to another can be 1.7 ms or better. [ABSTRACT FROM PUBLISHER]

We study the coordinated transmission problem in cooperative cellular networks where a cluster of base stations forms a virtual cell to serve a mobile station (MS). The performance of such an MS-centric virtual cell network is dictated by the beamformer that enables to suppress interference; however, designing a beamformer is highly challenging due to the coupled nature of interference and desired signals under arbitrarily formed virtual cells. We develop a new formulation of the beamforming problem for sum-rate maximization in virtual cell networks and analyze the structure of its optimal solutions. Based on this analysis, we develop a beamforming algorithm that can balance between desired signal maximization and interference minimization, so as to maximize the sum-rate. We show through extensive simulations that our balanced beamforming algorithm mitigates edge user effect and outperforms existing algorithms in various scenarios where virtual cells are allowed to overlap. [ABSTRACT FROM PUBLISHER]

Due to the tradeoff between capacity and fairness in a wide variety of networks, increasing one objective may deteriorate the other. This paper investigates the possibility of improving capacity and fairness at the same time, specifically in two-hop cellular networks. First, we prove that an achievable capacity region can be enlarged by using relay, i.e., the capacity and fairness tradeoff relationship is alleviated. To achieve the Pareto-efficient boundary of this enlarged capacity region, an appropriate scheduling algorithm should be developed. Thus, second, we propose a generalized opportunistic scheduling algorithm for relaying mode that can improve both capacity and fairness. Furthermore, we propose a heuristic algorithm with low complexity and signaling overhead for relaying mode. Extensive simulations under various configurations demonstrate that the proposed algorithm not only increases the throughput of each user but also effectively alleviates unfairness among users. [ABSTRACT FROM PUBLISHER]

A triple-mode class-AB balanced linear power amplifier (PA) is realized in standard 0.18-\mu\ m CMOS technology. For the average efficiency enhancement, the triple-mode operation realizes a switched-quadrature coupler with a balanced topology to achieve robust load insensitivity. The PA and RF switches uniquely utilize the isolation port of the switched-quadrature coupler as a signal path in a low-power (LP) mode of operation, and the incorporated output matching network satisfies the \vert\Gamma\vert=1 condition from the quadrature coupler in the LP mode while providing the necessary load-pull impedance from the PA output side in the high-power (HP) mode. To obtain low loss and high quality factor (Q) of the passive output-combining network, a transformer-based quadrature coupler is implemented using a silicon-based integrated passive device process. With a 3.4-V power supply, the PA transmits a maximum output power of 28.4 dBm with 40.7% of power-added efficiency (PAE) and linear output power up to 26.6 dBm with 35% of the PAE using a 3-GPP WCDMA modulated signal. With the triple-mode operation, a PAE at 16 dBm is enhanced from 11.1% to 17%, and 47 mA of quiescent current is saved. The PA also shows robust operation under 2.5:1 of VSWR condition, achieving 1 dB of the gain variation and less than 3.9 dB of ACLR variation. This work demonstrates the potential of a highly efficient CMOS PA for WCDMA applications. [ABSTRACT FROM AUTHOR]

In this paper, a linear CMOS power amplifier (PA) with high output power (34-dBm saturated output power) for high data-rate mobile applications is introduced. The PA incorporates a parallel combination of four differential PA cores to generate high output power with good efficiency and linearity. To implement an efficient on-chip power combiner in a small form-factor, we propose a parallel-series combining transformer (PSCT), which mitigates drawbacks and limitations of conventional power-combining transformers such as a series combining transformer (SCT) and a parallel combining transformer (PCT). Using the proposed PSCT, a two-stage class-AB PA is designed and fabricated in a 0.18-\mu\m CMOS technology. The PA achieves a P 1∼dB of 31.5 dBm , a P sat of 34 dBm, and a P linear of 23.5 dBm with a peak PAE of 34.9% (peak drain efficiency of 41%) at the operating frequency of 2.4 GHz . A detailed analysis of the proposed PSCT is introduced along with comparisons to the conventional monolithic power-combining transformers. A design methodology of the integrated CMOS PA is also presented. [ABSTRACT FROM AUTHOR]

A dual-mode CMOS power amplifier (PA) with an integrated tunable matching network is presented. A switched capacitor is fully analyzed to implement a tunable matching network in terms of power-handling capability, tuning ratio, quality factor, and linearity. Based on the presented consideration, a 3.3-V 2.4-GHz fully integrated CMOS dual-mode PA is implemented in a 0.18-\mum CMOS process. The PA has two power modes, high-power and low-power (LP), and each mode is optimally matched by the tunable matching network. The LP mode enables more than 50% dc current reduction from 0- to 10-dBm power range. The improved efficiency in this study is approximately twice that of other multimode CMOS PAs reported thus far. [ABSTRACT FROM PUBLISHER]

This brief presents a regulated charge pump (CP) with an integrated optimum power point tracking (OPPT) algorithm designed for indoor solar energy harvesting. The proposed OPPT circuit does not require a current sensor that consumes power proportionally to the load. The solar cell voltage is regulated at the optimum power point; the CP output is regulated according to the target voltage. The controller of the OPPT circuit and CP dissipates only 450 nW; thus, the proposed technique is appropriate for indoor solar energy harvesting applications under dim lighting conditions. [ABSTRACT FROM PUBLISHER]

Efficiency degradation effects of power combining transformers with partially disabled inputs are quantitatively analyzed. To improve efficiencies in lower-power modes of a multi-mode class-AB power amplifier (PA), a discrete resizing technique is introduced in combination with a parallel-combining transformer (PCT). The two-stage PA implemented in a 0.18-\mu\m CMOS technology also includes varactor-based tunable matching circuits. The design method involves parallel-combining of two power stages, each of which are divided into three sub-cells to facilitate discrete resizing. The parallel-combining of concurrently resized power cells minimizes undesired power loss through the transformer and helps the PA to utilize the transformer efficiency maximally independent of the number of combining cells. When operating in the high-power mode, the PA exhibits a peak output power of 31 dBm with a PAE of 34.8%. Power back-offs are realized by discretely turning off parallel sub-amplifier cells concurrently, achieving output power levels of 26 dBm and 22.3 dBm with respective PAE of 22.5% and 15%. The EVM has been measured with IEEE 802.11g WLAN and 802.16e WiMAX modulated signals in three operation modes. In the high-power mode, the PA dissipates 590 mA from a 3.3 V supply. [ABSTRACT FROM PUBLISHER]

Presents a study which synthesized ferromagnetic exchange-spring nanocomposite thin films from sputter-deposited cobalt platinum. Experimental details; Results and discussion; Conclusions.