Search

In 3D integration, interconnections between stacked dies are ensured by conductive through silicon vias. Electrical conduction is achieved via coating the vias sidewalls with a metal, such as tungsten. In this work we have compared thermal-dependent stress of thin tungsten films deposited either in full plate oron vias sidewalls. The comparison of stress measurements at room temperature and during heating cycles reveals large differences between full plate and vias samples. At room temperature, in the vias samples, the stress is a factor 4 less than it is in the full plate sample, with both values indicating a tensile stress. While a thermo-elastic behavior is expected for the full plate sample, no stress evolution as a function of temperature is observed in the case of the vias samples.

Germanium tin (GeSn) is under equilibrium a two phase (Ge + Sn) system. Single phase GeSn alloys are important for silicon based heterostructure devices as stressors for Ge channels and as candidates for direct/indirect band cross-over. Such alloys would allow superior Ge channel metal oxide semiconductor devices and optoelectronic infrared circuits on a Si substrate. Preparation of GeSn layers is possible at low growth temperatures. We discuss the challenges caused by the non-equilibrium growth and the limitations of low temperature epitaxy. Main challenges and limitations are the surface segregation, precipitations and defect accumulation in low temperature epitaxy. The problem of high lattice mismatch between Si and GeSn (> 4%) can be solved using virtual substrates with strain relaxed Ge buffer layers. The lattice mismatch can be reduced to 1% and below. Growth of pseudomorphic GeSn layers on Ge buffers/Si substrate was investigated. The samples were characterized by X-ray methods and Raman spectroscopy. High device process stability was achieved up to 600 °C annealing and documented by Raman spectroscopy. Fabrication of a detector test device demonstrated feasibility for optoelectronic applications with extended infrared range.

The processing of Si-based devices induces very high local strains in silicon. This strain field is worth investigating in particular in Shallow Trench Isolation, which is a key step in the production of non-volatile-memories and transistors. In this study we investigate by high high-resolution X-ray diffraction the periodic strain field induced in silicon by the STI process. High-resolution X-ray diffraction is shown to be very sensitive ( − 4 ) to local strains and has the distinct advantage of being non-destructive. Investigated samples are periodic arrays of SiO 2 -filled trenches in single crystal (001) Si. The trenches are etched either along [100] or along [110]. The experiments have been performed on a 4 circles goniometer with a laboratory source. We have recorded Si 004 and asymmetric Si 224 or Si 404 reciprocal space maps in order to extract axial strains in the 3 directions. The trenches array induces a periodic strain field in silicon, which gives rise to distinct satellites in reciprocal space. The intensity of these satellites is related to the strain field. We also performed elastic calculations with a finite element modelling code. Finally structure factor calculations are performed using the displacement field determined from mechanical modelling. We focus here on the effect of silicon elastic anisotropy on the strain field in 580 nm and 200 nm period samples. The influence of line crystallographic orientation ([100] or [110]) on the strain field is evaluated by finite element modelling and compared with experimental ones. The silicon anisotropy has a weak effect on strain and is compensated by process variations due to the line orientation.