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Stress measurements in tungsten coated through silicon vias for 3D integration
- Source :
- Thin Solid Films. 530:91-95
- Publication Year :
- 2013
- Publisher :
- Elsevier BV, 2013.
-
Abstract
- In 3D integration, interconnections between stacked dies are ensured by conductive through silicon vias. Electrical conduction is achieved via coating the vias sidewalls with a metal, such as tungsten. In this work we have compared thermal-dependent stress of thin tungsten films deposited either in full plate oron vias sidewalls. The comparison of stress measurements at room temperature and during heating cycles reveals large differences between full plate and vias samples. At room temperature, in the vias samples, the stress is a factor 4 less than it is in the full plate sample, with both values indicating a tensile stress. While a thermo-elastic behavior is expected for the full plate sample, no stress evolution as a function of temperature is observed in the case of the vias samples.
- Subjects :
- Materials science
Silicon
Metals and Alloys
chemistry.chemical_element
Surfaces and Interfaces
Chemical vapor deposition
engineering.material
Tungsten
Surfaces, Coatings and Films
Electronic, Optical and Magnetic Materials
Stress (mechanics)
Coating
chemistry
Sputtering
X-ray crystallography
Materials Chemistry
engineering
Composite material
Electrical conductor
Subjects
Details
- ISSN :
- 00406090
- Volume :
- 530
- Database :
- OpenAIRE
- Journal :
- Thin Solid Films
- Accession number :
- edsair.doi...........8a35b9d1b9c602484cd0456df38436a4