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Space laser communication is moving in a wider bandwidth, greater distances, is more accurate and more narrow laser communication beam direction, faster bandwidth as well as communication interface chip high-speed clock more demanding requirements of the low frequency noise, and good reliability, small size and low power consumption characteristics. Production of ADI's ADF4350 integrated voltage-controlled oscillator (VCO) bandwidth frequency synthesizer just to meet this requirement clock frequency This paper describes the basic principles and operating characteristics of the broadband frequency synthesizer. In this paper we use CPLD to control the ADF4350 and give a control electric circuit with CPLD structure and based on Verilog program. Simulation and experimental results show that the lock-in effect is good, easy to control, and reliable performance. It is able to generate stable clock, suitable for applications in laser communication.

The new problems of traditional clock design in hierarchical mode were analyzed in this paper and a new method of clock design was proposed. A phase_sync signal was used as a bridge of top-level and sub-design in this method. It effectively prevents the 'damage' to the internal timing of sub-design caused by top-level timing closure. The application of this method avoids reset design of clock divider circuit and reduces the difficulty of physical design

Clock synchronization is a critical component in wireless sensor networks, as it provides a common time frame to different nodes. It supports functions such as fusing voice and video data from different sensor nodes, time-based channel sharing, and sleep wake-up scheduling, etc. Early studies on clock synchronization for wireless sensor networks mainly focus on protocol design. However, clock synchronization problem is inherently related to parameter estimation, and recently, studies of clock synchronization from the signal processing viewpoint started to emerge. In this article, a survey of latest advances on clock synchronization is provided by adopting a signal processing viewpoint. We demonstrate that many existing and intuitive clock synchronization protocols can be interpreted by common statistical signal processing methods. Furthermore, the use of advanced signal processing techniques for deriving optimal clock synchronization algorithms under challenging scenarios will be illustrated.

Digital clock network design becomes one of the key research topics with the circuit area and the operation frequence increased. In order to improve the performance of the long linear arrays photo detector (512 elements) readout circuit and reduce the control timing uncertainty, this paper presented an improved clock distribution network based on full-custom design methodology, which optimized the system clock chip distribution. The circuit chip has been fabricated using Chartered 0.35um CMOS process, and the chip size was 3*18mm 2 , which operated at 50MHz. Test results showed that the improved clock distribution network can effectively reduce the clock delay for more than 87% and had a good inter-channel consistency. The readout accuracy met the design requirements.

A novel 10Gbit/s all-optical packet clock extractor, which comprises a Fabry-Perot (F-P) filter and a semiconductor optical amplifier (SOA), is proposed in this paper. Low Finesse Fabry-Perot (F-P) filter was used to directly extract the packet clock from the data packet stream, which ensures that the clock locks fast and vanishes quickly. The clock, amplitude modulated as a result of low-Q filter, then goes into SOA to reduce the low-frequency amplitude noise. The impact of F-P filter and SOA on the locking and unlocking time of the packet clock is theoretically analyzed. The result shows that the locking time is reduced while the unlocking time is increased, due to the self-gain modulation (SGM) effect. We demonstrate instantaneous 10.075GHz clock extraction experimentally with the establishing time of about 8 code-periods and vanishing time of about 22 code-periods.

We propose the optical transceiver having reference clock generator and CDR with delayed data topology in this paper. The 125MHz reference clock of optical transmitter have been extracted from 10 × 250 Mb/s data arrays. The clock extraction of reference clock generator is achieved by summing the edge information of the each data. Moreover, our optical transmitter includes 2-stacks NMOS serializer scheme rather than 3-stacks conventional scheme to achieve high speed operation. In optical receiver design, we employ a novel CDR with delayed data topology to overcome the problems in conventional CDR such as instability in locking state, nonlinearity output proportional to phase difference, false locking at harmonic frequency. The optical transceiver is designed by using of 0.35μm CMOS technology.

In this work, we demonstrate clock recovery from a patterned 160Gb/s optical-time-division-multiplexed (OTDM) return-to-zero (RZ) data stream. A cascaded LiNbO 3 Mach-Zehnder modulator is employed as an efficient optical-electrical mixer. A phase-locked-loop (PLL) is used to lock the cross-correlation component between the optical signal and a local oscillating signal. As a result, clock signal at 10GHz is extracted from the 160Gb/s optic al TDM signal. The measured root-mean-square (RMS) timing jitter of the 10GHz clock signal is ~ 130 fs. Keywords : Clock Recovery, Cascaded Modulator INTRODUCTION In ultra high speed optical communication networks, clock recovery is an essential element for any optical access node because it synchronizes the receiver decision circuitry with the incoming data stream 1 . Therefore, a stable clock source with low jitter characteristic 2 at the receiver end is required. However, due to the speed limitation of electrical circuits, at data rates beyond ~ 40 Gb/s, it becomes increasingly difficult to perform the stable clock recovery electronically. Optical clock recovery techniques that can be scaled to data rates of many tens of Gb/s to > 100 Gb/s will be a prerequisite to high data rate communication links of the future. For the optical clock recovery systems, the key steps are Optical-Electric (OE) mixing and cross-correlation detection. One approach to high-speed clock extraction is the injection mode locking technique, in which optical clock signal is obtained by launching the pulse trains into the cavity of a self-pulsating laser

Complexity of clock generator is one of the most important parameters in the design and optimization of switched-capacitor (SC) finite impulse response (FIR) filters. There are different SC FIR filter architectures. Some of them need a simple clock generator but the others require a quite complicated multiphase clock system. In the latter case an external clock system (i.e., outside the integrated circuit) is unrealistic because of a great number of the required external pins. We have implemented various SC FIR filter architectures together with complex internal clock generators in the CMOS 0.8 μm and 0.35 μm technologies. One of the most important problems in the design process was the optimization of waveforms and widths of the clock impulses. SC FIR filters are very sensitive to parameters of clock systems. Thus the clock generators must be designed very precisely. We demonstrate results of the design of the 64-phase clock generator for a programmable rotator SC FIR filter. In our approach the width of the clock impulses is controlled by two external signals. This is a very convenient solution, because optimization of the clock impulses, which was difficult in other approaches, is currently much easier. The internal clock generator area is ca. 0.15 mm 2 in the CMOS 0.35 μm technology, i.e., only 7 % of the entire SC FIR filter chip area.

Nowadays it is not possible to neglect the delay of interconnection lines. The die size is rising very fast, and the delay of the interconnection lines grows quadrically with it. Also, the fact that the gate delay keeps getting smaller increases the importance of the delay of the interconnection lines. The delay of the clock lines is specially important: If the clock skew is underestimated and the clocking scheme is not properly designed, then the system may not work under any clock frequency. In this paper we evaluate the timing performance of three skew-tolerant clocking schemes. These schemes are the well known Master-Slave clocking scheme (MS) and two schemes developed by the authors: Parallel Alternating Latches Clocking Scheme (PALACS) and four-phase Parallel Alternating Latches Clocking Scheme (four-phase PALACS). To carry out these analysis, the authors introduce new algorithms to obtain the clock waveforms required by a synchronous sequential circuit. Separated algorithms were developed for every clocking scheme. The algorithms take a set of timing parameters as input and generate a chronogram of the circuit trying to minimise the clock period but ensuring the timing restrictions of the circuit are met for a given clock skew. Using these algorithms is it possible to draw a representation of the computation frequency as a function of the clock skew for every clock scheme. Once we have estimated the timing parameters and the skew, these representations can help us to choose the best clocking scheme for our design.© (2005) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

A clock and data recovery (CDR) circuit is one of the crucial blocks in high-speed serial link communication systems. The data received in these systems are asynchronous and noisy, requiring that a clock be extracted to allow synchronous operations. Furthermore, the data must be "retimed" so that the jitter accumulated during transmission is removed. This paper presents a novel architecture of CDR, which is very tolerant to long sequences of serial ones or zeros and also robust to occasional long absence of transitions. The design is based on the fact that a basic clock recovery having a clock recovery circuit (CRC) and a data decision circuit separately would generate a high jitter clock when the received non-return-to-zero (NRZ) data with long sequences of ones or zeros. To eliminate this drawback, the proposed architecture incorporates a data circuit decision circuit within the phase-locked loop (PLL) CRC. Other than this, a new phase detector (PD) is also proposed, which was easy to accomplish and robust at high speed. This PD is functional with a random input and automatically turns to disable during both the locked state and long absence of transitions. The voltage-controlled oscillator (VCO) is also designed delicately to suppress the jitter. Due to the high stability, the jitter is highly reduced when the loop is locked. The simulation results of such CDR working at 1.25Gb/s particularly for 1000BASE-X Gigabit Ethernet by using TSMC 0.25μm technology are presented to prove the feasibility of this architecture. One more CDR based on edge detection architecture is also built in the circuit for performance comparisons.

Digital switching noise is the main source of on-chip noise in mixed-signal ICs. When many digital gates change state together, a large cumulative current spike flows through parasitic resistances and inductances and noise is also injected into the substrate, causing the sensitive analog portions of the design to malfunction. Many solutions have been proposed to alleviate this problem from both the analog and the digital domain. Some current mode families are used in low noise applications, but are strongly unsuited for low power applications, due to its static power consumption. In this paper we propose a set of techniques to reduce the switching noise generated by the digital circuitry, based on classical digital (static CMOS) methodologies at a circuit level. One of the most important sources of switching noise in large VLSI circuits is the clock-driven circuitry and the clock generation and distribution logic. It is well known for the mixed-signal community that harmonics of clock signal are easily injected in the analog part. This paper analyzes how some actuations like the insertion of buffers, the suited placement and routing of the clock tree cells, as well as the suited sizing of devices can save switching noise. In fact different solutions for the clocking logic generate very different results for switching noise. This paper faces the analysis and design of clock generation and distribution logic oriented towards low noise applications. Some illustrative examples will shown the feasibility of the proposed solutions, and some useful design guidelines will be proposed for the community of digital designers.

Nowadays clock recovery units are key elements in high speed digital communication systems. For an efficient operation, this units should generate a low jitter clock based on the NRZ received data, and be tolerant to long absence of transitions. Architectures based on Hogge phase detectors have been widely used, nevertheless, they are very sensitive to jitter of the received data and they have a limited tolerance to the absence of transitions. This paper shows a novel high speed clock recovery unit based on a phase aligner. The system allows a very fast clock recovery with a low jitter, moreover, it is very resistant to absence of transitions. The design is based on eight phases obtained from a reference clock running at the nominal frequency of the received signal. This high speed reference clock is generated using a crystal and a clock multiplier unit. The phase alignment system chooses, as starting point, the two phases closest to the data phase. This allows a maximum error of 45 degrees between the clock and data signal phases. Furthermore, the system includes a feed-back loop that interpolates the chosen phases to reduce the phase error to zero. Due to the high stability and reduced tolerance of the local reference clock, the jitter obtained is highly reduced and the system becomes able to operate under long absence of transitions. This performances make this design suitable for systems such as high speed serial link technologies. This system has been designed for CMOS 0.25μm at 1.25GHz and has been verified through HSpice simulations.

This paper reviews recent results for clock recovery circuits operating at speeds in excess of 1 Gbit/sec or realized as multichannel arrays. The emphasis is on Synchronous Optical NETwork (SONET) type systems, their requirements, and the effect of the clock recovery circuits on system performance. Clock recovery approaches include filter based, phase-lockcd-loops, and all-optical methods.

This paper describes a board-level realization of 2.5 Gb/s clock and data regenerator circuit, where the clock recovery function is implemented by a phase locked loop configuration. In order to use a low cost commercially available voltage controlled oscillator (VCO) a Richman quadricorrelator frequency-difference discriminator has been designed. The resultant frequency and phase locked loop (FPLL), makes possible the frequency acquisition even if the VCO starting frequency were out of the PLL pull-in range. All components used are cheap commercially available silicon devices. Measurements, at 10-9 bit error rate, give an input electrical sensitivity less of 5 mVpp with 223-1 pseudo-random input data stream. The recovered clock jitter is compliant with SONET STM-16.© (1995) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

A high speed clock distribution network using free space optical interconnects with substrate mode holograms and high speed transmitter/receiver modules is described. An electrically compatible system with signal jitter less than 70/50 ps at 622/840 MHz is demonstrated. To improve the power consumption of receivers, a low noise receiver applying a resonant front end circuit is designed. The receiver performance is presented and the corresponding system issues are discussed.

In this communication we consider the use of a phase locked loop with signal injection (PLLI) in clock synchronization circuits. We show that by exploring the correlation between the I (in-phase) and Q (quadrature) components of the disturbance,the PLLI allows significant improvements in the output jitter. Numerical results are given tbr optical communications with RZsignaling which show considerable improvements relatively to a conventional PLL. Experimental measurements obtained witha Colpitts VCO designed to allow current injection are presented that demonstrate the effectiveness of the PLLI in exploring theI-Q correlation. I Introduction Clock SynchrOfliZatli)fl is a fundamental operation in digital communications. An accurate clock must be available at the receiverin order to pertorm the decisions at the most correct xints. The subject of clock synchronization has been widely studied and alarge number of structures lmve been proposed. In order to achieve optimum performance, the clock recovery problem is usually

A mixed signal Application-Specific Standard Product (ASSP) which integrates custom phase-locked loop (PLL) based clock recovery and clock synthesis functions with configurable logic cells provides a two-chip solution for 266 to 1062 Mbit/s Fiber Channel applications. The chipset performs parallel-to-serial and serial-to-parallel conversion, 8B/10B encoding/decoding functions, framing, and primitive signal/sequence generation and identification. The on-chip clock synthesis PLL generates the high-speed serial clock from a low-speed reference. The on-chip clock recovery PLL is capable of synchronizing directly to incoming digital signals, while simultaneously retiming and regenerating the data stream. The chips are designed using an advanced one-micron bipolar process with `Turbo' cells resulting in substantially reduced static power and output skews. Models for the PLL functions have been developed for use in logic simulation platforms. These models allow full chip-level and system-level simulation capabilities.

A 2500 gate mixed signal gate array has been developed that integrates custom PLL-based clock recovery and clock synthesis functions with 2500 gates of configurable logic cells to provide a single chip solution for 200 - 1244 MHz fiber based digital interface applications. By customizing the digital logic cells, any of the popular telecom and datacom standards may be implemented.

We report about the design of an optical intrachip clock distribution using an IR-laser diode 1 ocated at one edge of an electronic chip and 4 on-chip photoreceivers, all components connected via a reflective HOE. The high divergence angle of the laser beam and its oblique incidence onto the HOE together wfth the 4 fan-out directions require HOE-feature sizes which are in the order of the operation wavelength X0.86 tm. This study considers both multiplex and multifacet computer-generated HOEs . The pattern complexity, the respective pattern resolutions, the beam rouung abilities and the spot quality of the focused output beams are discussed. A calculation method for the estimation of the alignment tolerances is explained and the results will show that our arrangement is feasible using mounting techniques based on micromechanics in preferential etched silicon.

Controlling system clock skew at the desired system cycle time is the major challenge in the design of a clock distribution network. Optical techniques offer a potential alternative to conventional electrical means for distributing clock signals. For optical clock distribution, the limiting factors are the level of optical power available to the photodetectors and the timing uncertainty (skew) in optical receivers. This paper presents an analysis for receiver skew in terms of the RMS timing jitter, static skew and photodetector-induced skew. Based on this analysis, an optical fanout model is developed relating system skew to the received optical power for various Si and GaAs receiver configurations. This model predicts that, for high optical fanout levels (in the order of 100), system clock skew in the range of 100 to 200ps is achievable using avalanche photo-diode receivers. Skew measured for an experimental system was 120 ps, correlating well with the analytical model.

Parallel computing structures consist of many processors operating simultaneously. If a concurrent structure is regular, as in the case of a systolic array. it may be convenient to think of all processors as operating in lock step. This synchronized view, for example, often makes the definition of the structure and its correctness relatively easy to follow. However, large, totally synchronized systems controlled by central clocks are difficult to implement because of the inevitable problem of clock skews and delays. An alternative means of enforcing necessary synchronization is the use of self-timed, asynchronous schemes, at the cost of increased design complexity and hardware cost. Realizing that different circumstances call for different synchronization methods, this paper provides a spectrum of synchronization models; based on the assumptions made for each model, theoretical lower bounds on clock skew are derived, and appropriate or best-possible synchronization schemes for systolic arrays are proposed. In general, this paper represents a first step towards a systematic study of synchronization problems for large systolic arrays. One set of models is based on assumptions that allow the use of a pipelined clocking scheme, where more than one clock event is propagated at a time. In this case, it is shown that even assuming that physical variations along clock lines can produce skews between wires of the same length, any one-dimensional systolic array can be correctly synchronized by a global pipelined clock while enjoying desirable properties such as modularity, expandability and robustness in the synchronization scheme. This result cannot be extended to two-dimensional arrays, however--the paper shows that under this assumption, it is impossible to run a clock such that the maximum clock skew between two communicating cells will be bounded by a constant as systems grow. For such cases or where pipelined clocking is unworkable, a synchronization scheme incorporating both clocked and "asynchronous" elements is proposed.

In order to regenerate pulses in a transmission system for pulse coded signals, a clock signal should be available. In self timing repeaters, this clock signal is derived from the baseband information signal itself. This includes filtering by means of a resonant circuit (SAW filter) or by a phase lock loop (PLL).

In synchronous systems, clock signals are used to maintain the order of occurance of events as well as defining the time frame in which logic is performed. Clock skew, the variance in arrival times of the same state of the clock signal to various parts in the system, is being identified as one of the main limitations to system performance. In this paper, we analyze an optical alternative for clock distribution. To demonstrate the feasibility of optical clock distribution, an experimental system has been designed and implemented to achieve a clock skew less than 200 psec.

The use of optical wavelength division multiplexing (WDM) for the simultaneous transmission of clock and data signals has possible application in the interconnection of communications equipment. This paper presents experimental results from transmitting clock and data signals through a single-mode optical fibre using WDM and highlights a technique to overcome phase mis-alignment between the clock and data signals at the point of retiming.