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A 640×512 readout integrated circuit (ROIC) with 15um pixel pitch for middle-wave infrared focal plane arrays (MWIR FPAs) is designed in this paper. The 15um pixel pitch presents several challenges to the ROIC design, such as achieving the required charge storage capacity to preserve the high SNR and reading or processing the pixel signals correctly to achieve the required frame rate. A novel structure that four neighboring pixels share one integration capacitor is presented as a feasible approach to getting a large charge capacity in the limited pixel area. Meanwhile, the pixel circuit chooses the direct injection (DI) which occupies the small layout area as the input stage for MW and contains two sample and hold modules to further increase the charge capacity. Moreover,the peripheral analog signal chain circuit, which is composed of a PMOS source follower, a column amplifier and the complementary output stage, is designed to transfer the signals from unit cell with less voltage loss,lower power consumption, lower noise and higher linearity. More importantly, in our design, only half chain circuit are required therefore the corresponding power consumption will be reduced greatly. In order to accommodate this design, two kinds of pixel signal readout sequences are compared. By adopting the 0.18um 1P6M mixed signal CMOS process, the circuit architecture can make the effective charge capacity of 13Me- per pixel with 1.38V final output range. The 4×4 circuit layout will be fulfilled as a whole and in this way the effective integration capacitor can be increased. According to the simulation results, this circuit works well under 3.3V power supply and achieves 10MHZ readout rate and less than 0.1% nonlinearity.

New large scale foundry processes continue to produce reliable products. These new large scale devices continue to use industry best practice to screen for failure mechanisms and validate their long lifetime. The Failure-in-Time analysis in conjunction with foundry qualification information can be used to evaluate large format device lifetimes. This analysis is a helpful tool when zero failure life tests are typical. The reliability of the device is estimated by applying the failure rate to the use conditions. JEDEC publications continue to be the industry accepted methods.

We present our approach towards an automated design framework for integrated photonics and optoelectronics, based on the experience of developing VPIcomponentMaker Photonic Circuits. We show that design tasks imposed by large-scale integrated photonics require introducing new “functional” types of model parameters and extending the hierarchical design approach with advanced parameter scripting capabilities. We discuss the requirements imposed by the need for seamless integration between circuit-level and device-level simulators, and illustrate our approach for the combination of VPIcomponentMaker Photonic Circuits and VPImodeDesigner. We show that accurate and scalable circuit-level modeling of large-scale photonic integrated circuits requires combination of several frequency- and time-domain simulation techniques (scattering-matrix assembly, transmission-line models, FIR and IIR digital filters, etc) within the same circuit simulation. We extend the scattering-matrix assembly approach for modeling linear electronic circuits, and motivate it being a viable alternative to the traditional modified nodal analysis approach employed in SPICE-like electronic circuit simulators. Further, we present our approach to support process design kits (PDK) for generic foundries of integrated photonics. It is based on the PDAFlow API which is designed to link different photonic simulation and design automation tools. In particular, it allows design and optimization of photonic circuits for a selected foundry with VPIcomponentMaker Photonic Circuits, and their subsequent export to PhoeniX OptoDesigner for layout verification and GDSII mask generation.

The ultraviolet imaging sensors consist of two important parts: the array of detectors and the read out integrated circuits. Along with the demand for the fine resolution, large input dynamic range and high integration degree of the imaging sensors, the functions of read out integrated circuits are becoming more and more important. The on chip analog to digital conversion is the main directions of research on this area. In this paper, we presented a new digital read out integrated circuits for ultraviolet imaging sensors. The proposed circuits have an analog to digital converter in each pixel, which enable the parallel analog to digital conversion of the whole pixel array. The developed circuits have a 50um×50um pixel area with a 128×128 size, and are designed in a 0.35um four metal double poly mixed signal CMOS process. The simulation results show that the designed analog to digital converter has an accuracy of 0.2mV and can achieve the dynamic range of 88dB. The proposed circuits realize the low noise and high speed digital output of read out integrated circuits for ultraviolet imaging sensors.

The implementation of an effective readout integrated circuit for 320 x 256 middle-and long-wave infrared focal plane arrays (MLIR FPAs) imaging system is detailed in this paper. The key purpose of this design is transferring the signals from dual-color detectors sequentially with effectiveness including lower noise, less voltage loss, lower power consumption, higher linearity, higher speed etc. A double sharing capacitor (DSC) structure is adopted as a solution to how to make a trade-off between the areas of capacitors and the main MOSFETs structures. Compared to the traditional charge transferring, a zero-charge-loss mechanism is applied in this circuit to guarantee a high voltage transferring efficiency. A three-stage cascaded unit gain amplifiers is used to get a high drive capability and good linearity. Meanwhile, a simple but effective power management is introduced to the section of arrays and the first output stage to ensure acceptable power consumption. Moreover, a testing line with adjustable current source is added aside to fulfill the effective testability. Now, the chip has been fabricated with the 0.35um 2P4M mixed signal technology and finished basic testing process. According to the testing results, the whole chip presents a sensitive response to illumination and the output voltage steps are clearly legible at 2.5MHz data transmission rate. As it is expected, this structure achieves 100f/s frame frequency and less than 1% nonlinearity under 5V power supply. However, the output swing reduced to 2V at room temperature of which the reason should be researched further. The total power consumption reaches 170mW.

Since the technology trend of the third generation IRFPA towards resolution enhancing has steadily progressed,the pixel pitch of IRFPA has been greatly reduced.A 640×512 readout integrated circuit(ROIC) of IRFPA with 15μm pixel pitch is presented in this paper.The 15μm pixel pitch ROIC design will face many challenges.As we all known,the integrating capacitor is a key performance parameter when considering pixel area,charge capacity and dynamic range,so we adopt the effective method of 2 by 2 pixels sharing an integrating capacitor to solve this problem.The input unit cell architecture will contain two paralleled sample and hold parts,which not only allow the FPA to be operated in full frame snapshot mode but also save relatively unit circuit area.Different applications need more matching input unit circuits. Because the dimension of 2×2 pixels is 30μm×30μm, an input stage based on direct injection (DI) which has medium injection ratio and small layout area is proved to be suitable for middle wave (MW) while BDI with three-transistor cascode amplifier for long wave(LW). By adopting the 0.35μm 2P4M mixed signal process, the circuit architecture can make the effective charge capacity of 7.8Me - per pixel with 2.2V output range for MW and 7.3 Me - per pixel with 2.6V output range for LW. According to the simulation results, this circuit works well under 5V power supply and achieves less than 0.1% nonlinearity.

A 128×128 matrix readout integrated circuit (ROIC) for 15×15 μm 2 InGaAs focal plane array (FPA) is reported in this paper. Capacitive-feedback Trans-Impedance Amplifier (CTIA) and correlated double sampling (CDS) are both involved in ROIC pixel which dissipates 90nW and has a full-well-capacity (FWC) of about 78,000 e-. Noises of ROIC pixel are analyzed and distribution method of capacitors in pixel is discussed in order to obtain low-noise performance. In column buffer circuit, a new pre-charging technique is developed to realize readout rate of 20 MHz with low power consumption. The ROIC is fabricated with 0.18-μm 3.3 V mixed signal CMOS process. Test results show that the ROIC has an equivalent input noise of about 181e- and can achieve a readout rate of 20 MHz.

ePix100 is the first variant of a novel class of integrating pixel ASICs architectures optimized for the processing of signals in second generation LINAC Coherent Light Source (LCLS) X-Ray cameras. ePix100 is optimized for ultra-low noise application requiring high spatial resolution. ePix ASICs are based on a common platform composed of a random access analog matrix of pixel with global shutter, fast parallel column readout, and dedicated sigma-delta analog to digital converters per column. The ePix100 variant has 50μmx50μm pixels arranged in a 352x384 matrix, a resolution of 50e- r.m.s. and a signal range of 35fC (100 photons at 8keV). In its final version it will be able to sustain a frame rate of 1kHz. A first prototype has been fabricated and characterized and the measurement results are reported here.

The paper deals with the opportunity to introduce “Not strictly TEM waves” Synthetic detection Method (NTSM), consisting in a Three Axis Digital Beam Processing (3ADBP), to enhance the performances of radio telescope and sensor systems. Current Radio Telescopes generally use the classic 3D “TEM waves” approximation Detection Method, which consists in a linear tomography process (Single or Dual axis beam forming processing) neglecting the small z component. The Synthetic FEED ARRAY three axis Sensor SYSTEM is an innovative technique using a synthetic detection of the generic “NOT strictly TEM Waves radiation coming from the Cosmo, which processes longitudinal component of Angular Momentum too. Than the simultaneous extraction from radiation of both the linear and quadratic information component, may reduce the complexity to reconstruct the Early Universe in the different requested scales. This next order approximation detection of the observed cosmologic processes, may improve the efficacy of the statistical numerical model used to elaborate the same information acquired. The present work focuses on detection of such waves at carrier frequencies in the bands ranging from LF to MMW. The work shows in further detail the new generation of on line programmable and reconfigurable Mixed Signal ASIC technology that made possible the innovative Synthetic Sensor. Furthermore the paper shows the ability of such technique to increase the Radio Telescope Array Antenna performances.

High frame rate imaging for applications such as meteorological forecast, motion target tracking require high-speed Read-Out Integrated Circuit (ROIC). In order to achieve 10 KHz of frame rate, this paper analyzes the bandwidth of Capacitive-feedback Trans-Impedance Amplifier (CTIA) in ROIC which is the dominant bandwidth-limiting node when interfaced with large InGaAs detector pixel capacitance of about 10pF. A small-signal model is presented to study the relationship between integration capacitance, detector capacitance, transconductance and CTIA bandwidth. Calculation and simulation results show explicitly how the series resistance at the interface restricts the frame rate of Focal Plane Arrays (FPA). In order to achieve low-noise performance at a high frame rate, this paper describes an optimal solution in ROIC design. A prototype ROIC chip (DL7) has been fabricated with 0.5-μm mixed signal CMOS process and interfaced with InGaAs detector arrays. Test results show that frame rate is above 10 KHz and ROIC noise is around 270 e-, near identical to the design value.

Miniature robots present a number of challenging problems in controls, as they often exhibit nonlinear dynamics and have strict power and size constraints. These constraints limit the sensing and processing capabilities drastically. Many control techniques require knowledge of the robot’s position, so the position must be estimated when it cannot be sensed directly. We report a mixed signal odometry circuit that maps motor commands to estimated and predicted changes in position in Euclidean space ( x, y, θ ). We compare the mixed-signal implementation with other approaches and find that the mixed-signal implementation offers significant reductions in power consumption at an acceptable loss of precision.

This paper proposes dual-mode buffer direct injection (BDI) and direct injection (DI) readout circuit design. The DI readout circuit has the advantage of being a simple circuit, requiring a small layout area, and low power consumption. The internal resistance of the photodetector will affect the photocurrent injection efficiency. We used a buffer amplifier to design the BDI readout circuit since it would reduce the input impedance and raise the injection efficiency. This paper will discuss and analyze the power consumption, injection efficiency, layout area, and circuit noise. The circuit is simulated using a TSMC 0.35 um Mixed Signal 2P4M CMOS 5 V process. The dimension of the pixel area is 30×30 μm. We have designed a 10×8 array for the readout circuit of the interlaced columns. The input current ranges from 1 nA to 10 nA, when the measurement current is 10 pA to 10 nA. The integration time was varied. The circuit output swing was 2 V. The total root mean square noise voltage was 4.84 mV. The signal to noise ratio was 52 dB, and the full chip circuit power consumption was 9.94 mW.

A readout integrated circuit (ROIC) for 320× 256 middle-wave and long-wave infrared focal plane arrays, is studied in this paper. This circuit operates in integrating-while-reading (IWR) mode with the frame rate higher than 100fps. A novel DI structure is used for signal acquisition of middle wave while BDI structure for long wave. It is common that trade-offs always exist between chip area and performances in integrated circuits design. In order to get high injection efficiency for BDI structure with small area, a four-transistor amplifier with a gain of 82dB is designed. The charge capacity of ROIC is also a key performance parameter when considering the noise and the large middle-wave and longwave photocurrent (up to 5nA and 100nA, respectively). A structure named double sharing capacitors (DSC) presented in this paper will be an effective solution to getting a large capacity in the limited 50 μm x 50 μm pitch area. DSC means that each integrating capacitor has two kinds of shares. One is between the integrating capacitor and another integrating capacitor which is in the adjacent pixel, and the other is between the integrating capacitor and the holding capacitor in the same pixel. By adopting the 0.35μm 2P4M mixed signal process, the DSC architecture can make the total effective charge capacity as high as 70Me- per pixel with 3V output range. According to the simulation results, this circuit works well under 5V power supply and achieves 2.5MHz data transmission rate, less than 0.1% nonlinearity. Its total power consumption is less than 110mW.

InGaAs near-infrared (NIR) focal plane arrays (FPA) have important applications in space remote sensing. A design of 800×2 low-noise readout integrated circuit (T800 ROIC) with a pitch of 25 μm is presented for a dual-band monolithic InGaAs FPA. Mathematical analysis and transient noise simulations have been presented for predicting and lowering the noise in T800 ROIC. Thermal noise from input-stage amplifier which plays a dominant role in ROIC is reduced by increasing load capacitor under tradeoff and a low input offset voltage in the range of ±5 mV is obtained by optimizing transistors in the input-stage amplifier. T800 ROIC has been fabricated with 0.5-μm 5V mixed signal CMOS process and interfaced with InGaAs detector arrays. Test results show that ROIC noise is around 90 μV and input offset voltage shows a good correspondence with simulation results. 800×2 InGaAs FPA has a peak detectivity (D*) of about 1.1×1012 cmHz1/2/ W, with dynamic range of above 80dB.

New foundry processes continue to produce smaller features and new designs. These new devices must be screened to validate their usefulness for long lifetime use. The Failure-in-Time analysis in conjunction with foundry qualification information can be used to evaluate foundry device lifetimes. This analysis is a helpful tool when zero failure life tests are performed. The reliability of the device is estimated by applying the failure rate to the use conditions. JEDEC publications. 2,3,4 are the industry accepted methods.

Increasingly complex specifications for next-generation focal plane arrays (FPAs) require smaller pixels, larger array sizes, reduced power consumption and lower cost. We have previously reported on the favorable features available in the commercially available TowerJazz CA18 0.18mm mixed-signal CMOS technology platform for advanced read-out integrated circuit (ROIC) applications. In his paper, new devices in development for commercial purposes and which may have applications in advanced ROICs are reported. First, results of buried-channel 3.3V field effect transistors (FETs) are detailed. The buried-channel pFETs show flicker (1/f) noise reductions of ~5X in comparison to surface-channel pFETs along with a significant reduction of the body constant parameter. The buried-channel nFETs show ~2X reduction of 1/f noise versus surface-channel nFETs. Additional reduced threshold voltage nFETs and pFETs are also described. Second, a high-density capacitor solution with a four-stacked linear (metal-insulator-metal) MIM capacitor having capacitance density of 8fF/mm2 is reported. Additional stacking with MOS capacitor in a 5V tolerant process results in g50fC/mm2 charge density. Finally, one-time programmable (OTP) and multi-time programmable (MTP) non-volatile memory options in the CA18 technology platform are outlined.© (2012) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.

Sensors with long lifetimes are ideal for infrastructure monitoring. Miniaturized sensor systems are only capable of storing small amounts of energy. Prior work has increased sensor lifetime through the reduction of supply voltage , necessitating voltage conversion from storage elements such as batteries. Sensor lifetime can be further extended by harvesting from solar, vibrational, or thermal energy. Since harvested energy is sporadic, it must be detected and stored. Harvesting sources do not provide voltage levels suitable for secondary power sources, necessitating DC-DC upconversion. We demonstrate a 8.75mm 3 sensor system with a near-threshold ARM microcontroller, custom 3.3fW/bit SRAM, two 1mm 2 solar cells, a thin-film Li-ion battery, and integrated power management unit. The 7.7μW system enters a 550pW data-retentive sleep state between measurements and harvests solar energy to enable energy autonomy. Our receiver and transmitter architectures benefit from a design strategy that employs mixed signal and digital circuit schemes that perform well in advanced CMOS integrated circuit technologies. A prototype transmitter implemented in 0.13μm CMOS satisfies the requirements for Zigbee, but consumes far less power consumption than state-of-the-art commercial devices.

The device is controlled by TMS320F2812 microprocessor. It mainly includes signal acquisition circuit, keyboard circuit, Chinese / English LCD display circuit, the calendar clock circuits, alarm circuits, relay output circuit, communications interface circuits, DI / DO circuit, power circuit and CPU circuit and so on. In addition, the device integrates a sensor transmission circuit, so it can directly connect with temperature pressure sensors to achieve high-precision measurement and monitoring. According to needs of users, it can work in different modes without the additional controller respectively. The equipment can communicate with each other by CAN bus or RS485. It mainly can realize the control and analysis of equipment status, failure predication and diagnosis, information management, etc.

This paper proposes two kinds of readout integrated circuits for column and row interlaced dual-band infrared detectors. The experiments were simulated using TSMC 0.35μm Mixed Signal 2P4M CMOS process and operated at 3MHz clock rate. The pixel dimensions for two kinds of readout integrated circuits were also 30×30μm. The mid-wave and long-wave sense current was set from 1nA to 2nA and 6nA to 8nA, respectively. We designed a 40x16 array for the columns interlace readout circuit. The output voltage swing was 2.8V. The frame rate was 4.68kFPS. The total power consumption was less than 17.6mW. We also designed a 20x32 array for the row interlace readout circuit. The output voltage swing was 2.8V. The frame rate was 2.67kFPS. The total power consumption was less than 11.4mW. The power consumption increased when the column interlace frame rate reached the row interlace frame rate. The row interlace can decrease the layout area by sharing the column stage circuit, but the frame rate will drop to half of the single band frame rate.

The noises of CMOS readout integrated circuit (ROIC) for hybrid focal plane array (FPA) may occupy a great part of total noise in conditions that a low resistance or large capacitor detector interfacing with CTIA input stage. A novel low noise low power preamplifier with shared current-mirrors bias is designed. It has a gain of more than 90dB, which makes enough inject efficiency and low detector bias offset. Besides, it has strong detector bias control, because the shared current-mirror copies the DC current of the amplifier and generates the bias control voltage. A pixel level Correlated Double Sample circuits is designed in order to suppress the reset KTC noise and 1/f noise from preamplifier. An experimental chip of 30μm pitch 32×32 array was fabricated in standard 0.5μm CMOS mixed signal process. A few experimental structures are designed to study the allocating of layout area for low noise designing. The ROIC is bonded to an existing back-illuminated 30μm pitch InGaAs photodiode array with indium bump fabrication. The test of both the ROIC chips and InGaAs focal plane array is shown in this paper, and the contrast of different structure is shown and analyzed.

Nanometer CMOS processes have proven to be surprisingly effective for analog and RF design. New design techniques have greatly improved the efficiency of ADCs and RF interfaces and also enabled new flexibility. Moving to techniques that are more digital in nature allows fast and easy changes in architecture and performance. Furthermore, from the standpoint of energy efficiency there can be fundamental advantages to processing signals in the digital domain. This paper discusses digital dominant nanometer CMOS transmitter and receiver schemes that are the basis of flexible efficient wireless transceivers for the MAST platforms.

Defects and faults arise from physical imperfections and noise susceptibility of the analog circuit components used to create digital circuits resulting in computational errors. A probabilistic computational model is needed to quantify and analyze the effect of noisy signals on computational accuracy in digital circuits. This model computes the reliability of digital circuits meaning that the inputs and outputs and their implemented logic function need to be calculated probabilistically. The purpose of this paper is to present a new architecture for designing noise-tolerant digital circuits. The approach we propose is to use a class of single-input, single-output circuits called Reliability Enhancement Network Chain (RENC). A RENC is a concatenation of n simple logic circuits called Reliability Enhancement Network (REN). Each REN can increase the reliability of a digital circuit to a higher level. Reliability of the circuit can approach any desirable level when a RENC composed of a sufficient number of RENs is employed. Moreover, the proposed approach is applicable to the design of any logic circuit implemented with any logic technology.

Piezoresistive pressure sensor be made of semiconductor silicon based on Piezoresistive phenomenon, has many characteristics. But since the temperature effect of semiconductor, the performance of silicon sensor is also changed by temperature, and the pressure sensor without temperature drift can not be produced at present. This paper briefly describe the principles of sensors, the function of pressure sensor and the various types of compensation method, design the detailed digital compensation program for automotive pressure sensor. Simulation-Digital mixed signal conditioning is used in this dissertation, adopt signal conditioning chip MAX1452. AVR singlechip ATMEGA128 and other apparatus; fulfill the design of digital pressure sensor hardware circuit and singlechip hardware circuit; simultaneously design the singlechip software; Digital pressure sensor hardware circuit is used to implementing the correction and compensation of sensor; singlechip hardware circuit is used to implementing to controll the correction and compensation of pressure sensor; singlechip software is used to implementing to fulfill compensation arithmetic. In the end, it implement to measure the output of sensor, and contrast to the data of non-compensation, the outcome indicates that the compensation precision of compensated sensor output is obviously better than non-compensation sensor, not only improving the compensation precision but also increasing the stabilization of pressure sensor.

Dual-color(MWIR/SWIR)infrared focal plane array with sequence integration mode. It can export two bands photocurrent signal under irradiation. In order to deal with the signal electrical crosstalk problem which the unstable and large variant bias voltage of N-P+-N HgCdTe infrared detectors bring while two bands switch, A novel modified DI (MDI)circuit structure based on adjusting the bias voltage is presented. Through controlling timing sequence, MWIR and SWIR signal are integrated in turn and readout at the same time. The chips of 128×128 ROIC are designed and fabricated with 0.6 um double poly double metal mixed signal technology. The simulation shows right function of the circuit. Power dissipation of analog module is 20 mW, that of digital module is 10.25 uW and it has been tapped out.

Today's modular, mixed-signal CMOS process platforms are excellent choices for manufacturing of highly integrated, large-format read out integrated circuits (ROICs). Platform features, that can be used for both cooled and un-cooled ROIC applications, can include (1) quality passives such as 4fFμm2 stacked MIM capacitors for linearity and higher density capacitance per pixel, 1kOhm high-value poly-silicon resistors, 2.8μm thick metals for efficient power distribution and reduced I-R drop; (2) analog active devices such as low noise single gate 3.3V, and 1.8V/3.3V or 1.8V/5V dual gate configurations, 40V LDMOS FETs, and NPN and PNP devices, deep n-well for substrate isolation for analog blocks and digital logic; (3) tools to assist the circuit designer such as models for cryogenic temperatures, CAD assistance for metal density uniformity determination, statistical, X-sigma and PCM-based models for corner validation and to simulate design sensitivity, and (4) sub-field stitching for large die. The TowerJazz platform of technology for 0.50μm, 0.25μm and 0.18μm CMOS nodes, with features as described above, is described in detail in this paper.

An image quantization and mixed-signal processing technique presented in this paper significantly increases speed and resolution of image digitization while consuming minimum energy. It also performs image compression in the mixed signal domain. This has been achieved by exploiting strong correlation between neighboring pixels within each frame and between successive frames. The correlation is utilized by adaptive combining of several quantizers with different sampling rates and numbers of bits and by quantizing the entire image in a small fraction of frames while generating only discontinuity signals in the rest of the frames.

This paper discussed about a readout circuit for Quantum Dot Infrared Photodetector (QDIP) Focal-Plane-Array (FPA) imaging system. The readout circuit employed a modified regulated cascode circuit to stabilize the bias of QDIP. The readout circuit consisted of in-pixel dark current cancellation circuit, sensed current integration and in-pixel switch integration capacitor. The chip worked at 5V power supply and operated at 1MHz clock rate. Output voltage ranging from 2 volt to 4 volt was generated when the sensing current from 10nA to 100nA, the dark current was set up to 100nA. The total power consumption was less than 3.3 mW. The dimension of unit pixel was 30×30μm and the integration capacitance was about 0.24pF. The 8×8 pixels array readout circuit of in-pixel variable integration capacitors was implemented by using TSMC 0.35μm Mixed Signal 2P4M CMOS process.

In the design of Power Electronics converters, several approaches can be chosen for the implementation of the closed loop control. The use of a digital control loop implemented in a FPGA is becoming quite common. For the design of such a system, a simulation environment must be provided to check the digital and analog part working together. The simulation of both the analog and digital part is a very difficult task, which involves the simultaneous usage of an analog and a digital simulator, or the use of a mixed signal simulator. In this paper, we present a method to perform mixed signal simulation. The simulation is performed by linking PSIM analog simulator and ModelSim digital simulator. This method has proven to be very effective in the design of digital control circuits for power converters, implemented in FPGAs.

A novel 256×1 readout integrated circuit (ROIC) with simultaneous integration mode for two-color (MWIR/LWIR,MWIR/SWIR) n-p-P-P-N HgCdTe infrared detectors is presented in this paper. This ROIC features an input stage based on current mirror integration (CMI) structure, which separates MW (SW) photocurrent signal from mixed signals of LW and MW (MW and SW) and each waveband photocurrent signal is capable to be integrated in uncorrelated-simultaneous mode. A test chip of 256×1 ROIC is designed and fabricated with 0.6μm double poly double metal mixed signal technology. The chip test results prove right function of the circuit. It shows good performance of integration of MW and LW signals. The linearity of MW and LW output voltage- input current curve is over 99%. Power dissipation of the circuit is less than 50 mW. Readout clock frequency is up to 2 MHz.

The RENA-3 (R Readout E eadout Electronics for N lectronics Nuclear A uclear Applications) is a multi-channel mixed-signal integrated circuit (IC) developed for the readout of position-sensitive solid-state detectors with excellent energy resolution. We will present results of experiments characterizing its performance as used with a variety of spectroscopy-grade detectors currently available in the industry, notably CZT pixel arrays as well as other detector configurations. The merits of specific RENA-3 design features vis-a-vis different detector applications will also be discussed.

Aerial image simulation of interdigitated sidewall capacitor layouts and extraction of feature changes are used to estimate the parametric performance spread of DC Metal-Oxide-Metal (MOM) mixed signal capacitors as a function of the normalized lithographic resolution k1. Since minimum feature sizes are utilized, the variation of MOM capacitors is attributed to lithography spacing. In this paper, k1 of 0.8, 0.56, 0.40, and 0.28 are studied. The DC capacitance shows a worst-case variability of 42%. While line-end-shortening is a small fractional change in finger length and proves to be not a critical factor in variability, spacing width proves to be the main source of the variability in DC capacitance. Different annular illumination settings are explored for mitigating the variability in spacing width. Co-design of the pitch and illumination shows that for each k1, there is an optimal annular illumination radius. The optimal set of sigmas (i.e. sigma_in and sigma_out) can control the variability between linewidths and spacing widths to 20%.

Dynamic Voltage Scaling is a technique that reduces supply voltage and clock frequency, depending on system workload, with the aim of reducing power dissipation. This works is devoted to the modelling and integration in the same system level simulation environment of the analog DC-DC converter for Dynamic Voltage Scaling, the Dynamic Power Management and a test System on Chip with three Masters and two Slaves connected to the AMBA AHB bus. The DC-DC converter is described with a detail such that it is possible to verify the effect of the transient during the change of supply voltage on the performance of the DVS algorithm. SystemC and its extension SystemC-WMS have been used as description languages in which a system level description of the dynamic supply management coexists with the analog switching power converter and its control.

The design flow of Analog and Mixed Signal has to be improved. In a specific application, we propose a definition of the IP content and the structure of an IP-based library. The case study consists in the neuron-level integration of a complete system that emulates spiking neural networks. As it is often the case, the development of the analog part of the system requires the largest amount of time, due to the lack of formalism and automation in that domain. One solution to accelerate the analog design cycle is to re-use already designed blocks and accumulated design knowledge, which could be illustrated by the IP (Intellectual Property) concept. Indeed, an experience of about ten years and 19 designed ASICs allow now to have an accurate idea of the system hierarchy and the recurrent analog blocks, which is the basis of IP-based design. We will describe the IP-based library which has been developed for that specific application domain and show how it can be used to accelerate the design cycle of the next ASIC generation.

Based upon analog and digital circuits, the structure of the introduced circuit (Imager) is roundly incorporating an array of approximately 1.3 million pixels, placed on rows and columns. The signals, generated by pixels which are represented as CMOS sensors, are transmitted to a processing analog circuit consisting of a primary amplifying block, a secondary amplifying block, a programmable gain amplifier and an AD converter.

Technology development related to digital, antenna and RF subsystems for Microwave Radar Sensors like Synthetic Aperture Radar, Scatterometer, Altimeter and Radiometer is one of the major activities under ISRO's microwave remote sensing programme, since 1980s. These technologies are now being gainfully utilized for building ISRO's operational Earth Observation missions involving microwave sensors like Radar Imaging Satellite, RISAT SAR, Oceansat-2 Scatterometer, Megha-Tropiques, MADRAS and Airborne SAR for Disaster Management, DMSAR. Concurrently, advanced technology developments in these fields are underway to meet the major technological challenges of building ISRO's proposed advanced microwave missions like ultra-high resolution SAR's, Synthetic Aperture Radiometer (SARAD), Milli-meter and sub-millimeter wave sounders and SAR Constellations for Disaster management as well as Interferometric, Polarmetric and polarmetric interferometry applications. Also, these hardware are being designed with core radar electronics concept, in which the same RF and digital hardware sub-units / modules will be utilized to build different microwave radar sensors. One of the major and common requirements for all these active and passive microwave sensors is the moderate to highspeed data acquisition and signal processing system. Traditionally, the Data acquisition units for all these radar sensors are implemented as stand-alone units, following the radar receivers. For ISRO's C-band airborne SAR (ASAR) and RISAT high resolution SAR, we have designed and developed High Speed 8-bit ADC based I/Q Digitisers, operating at 30.814 MHz and 250 MHz sampling rates, respectively. With the increasing demand of wide bandwidth and ultra-high resolution in imaging and non-imaging radar systems, the technology trend worldwide is towards a digital receiver, involving bandpass or IF sampling, thus eliminating the need for RF down converters and analog IQ demodulators. In order to evolve a generic configuration for all the microwave sensors, we have initiated design and development of a generic L-band digital receiver, consisting of receiver elements (LNA, digital attenuator and Bandpass filter) followed by Analog-to-Digital Converter. The digitised data can then be output in parallel or serial format. Additionally, a digital signal processor performing tasks like data compression, convolution or correlation and formatting can also be integrated with this generic digital receiver. The front end of the receiver is wide-band, catering to bandwidths of upto 2 GHz while the digitisation rates are also of the order of 1-2 GHz. It is proposed to standardize the design and use this generic receiver for front end data acquisition of all the future microwave sensors. It will meet the digitisation requirements of 500 MHz to 1 GHz for ultra-high resolution (0.25-0.5 meter) SAR as well as direct sampling of the signal around 1.4GHz for L-band Synthetic Aperture Radiometer. After initial prototyping using discrete receiver elements and ultra-high speed 8-bit ADC, it will be taken up as a custom ASIC or multi-chip module consisting of RF MMIC's and a mixed signal ADC ASIC. These designs will be fabricated using InP, GaAs or SiGe process technologies at competent foundries like GATEC, SCL, Infineon/Germany, X-Fab/Germany and Ommic-Philips/France. This novel digital receiver will offer several advantages like flexibility, stability, reduced RF hardware and miniaturisation. This paper describes the ultra-high speed design requirements, configuration details and target specifications and salient features of this generic L-band digital receiver for ISRO's future spaceborne and airborne radar missions. It also addresses the associated signal integrity, EMI/EMC and thermal issues.

An automatic synthesis method of equivalent circuits of integrated circuit devices is described in the paper. This method is based on a physical approach to construction of finite-difference approximation to basic equations of semiconductor device physics. It allows to synthesize compact equivalent circuits of different devices automatically as alternative to, for example, sufficiently formal BSIM2 and BSIM3 models used in circuit simulation programs of SPICE type. The method is one of possible variants of general methodology for automatic synthesis of compact equivalent circuits of almost arbitrary devices and circuit-type structures of micro- and nanoelecronics [1]. The method is easily extended in the case of necessity to account thermal effects in integrated circuits. It was shown that its application would be especially perspective for analysis of integrated circuit fragments as a whole and for identification of significant collective physical effects, including parasitic effects in VLSI and ULSI. In the paper the examples illustrating possibilities of the method for automatic synthesis of compact equivalent circuits of some of semiconductor devices and integrated circuit devices are considered. Special attention is given to examples of integrated circuit devices for coarse grids of spatial discretization (less than 10 nodes).

Progress-to-date of a S-Ku band intelligent amplifier microsystem is presented. Performance objectives are 0.5 Watt with 30%-55% power added efficiency across the band using a total of 10 RF MEMS. GaAs-to-GaAs and Borosilicate-to-GaAs low temperature (

The optical components industry stands at the threshold of a major expansion that will restructure its business processes and sustain its profitability for the next three decades. This growth will establish a cost effective platform for the partitioning of electronic and photonic functionality to extend the processing power of integrated circuits. BAE Systems, Lucent Technologies, Massachusetts Institute of Technology, and Applied Wave Research are participating in a high payoff research and development program for the Microsystems Technology Office (MTO) of DARPA. The goal of the program is the development of technologies and design tools necessary to fabricate an application-specific, electronicphotonic integrated circuit (AS-EPIC). As part of the development of this demonstration platform we are exploring selected functions normally associated with the front end of mixed signal receivers such as modulation, detection, and filtering. The chip will be fabricated in the BAE Systems CMOS foundry and at MIT's Microphotonics Center. We will present the latest results on the performance of multi-layer deposited High Index Contrast Waveguides, CMOS compatible modulators and detectors, and optical filter slices. These advances will be discussed in the context of the Communications Technology Roadmap that was recently released by the MIT Microphotonics Center Industry Consortium.

Crosstalk from digital to analog in mixed-signal ICs is recognized as one of the major roadblocks for systems-on-chip (SoC) in future CMOS technologies. This crosstalk mainly happens via the semiconducting silicon substrate, which is usually treated as a ground node by analog and RF designers. The substrate noise coupling problem leads more and more to malfunctioning or extra design iterations. One of the reasons is that the phenomenon of substrate noise coupling is difficult to model and hence difficult to understand. It can be caused by the switching of thousands or millions of gates and depends on layout details. From the generation side (the digital domain), coping with the large amount of noise generators can be solved by macromodeling. On the other hand, the impact of substrate noise on the analog circuits requires careful modeling at the level of transistors and parasitics of layout, power supply, package, PCB, Comparison to measurements of macromodeling at the digital side and careful modeling at the analog side, shows that both the generation and the impact of substrate noise can be predicted with an accuracy of a few dB. In addition, this combination of macromodeling at the digital side and careful modeling at the analog side leads to an understanding of the problem, which can be used for digital low-noise design techniques to minimize the generation of noise, and substrate noise immune design of analog/RF circuits.

Oversampling Sigma-Delta modulators are commonly used in the design of high-resolution Analogue-to-Digital Converters (ADCs). The test of these ΣΔ modulators is a difficult and expensive task due to the need for the generation of a high-precision analogue test signal and the necessity of complex digital resources for the test response analysis. These problems can be overcome with the integration of the test in the chip by means of Built-In Self-Test (BIST) approaches. In this paper we present a BIST technique for high-precision ΣΔ modulators, by incorporating on-chip test signal generation and on-chip test response analysis capabilities. The approach, mostly digital, is based on the application of a binary stream as test stimulus and the re-use of the digital decimation filter present in a ΣΔ ADC for the test response analysis. The binary stimulus, which encodes a sinusoidal signal, is chosen to have a very high quality in the bandwidth of interest of the modulator. For the analysis of the test response, a high-precision sinusoidal signal is necessary as reference. This reference signal can be obtained from the same binary stimulus, by passing it directly to the digital decimation filter existing in the converter. Test response and sinusoidal reference signal are both compared by means of a sine-wave curve-fitting algorithm in order to obtain a measure of the SNDR (Signal-to-Noise-plus-Distortion Ratio). Simulation results show that this technique is capable of detecting the SNDR degradations caused by non-idealities in the modulator used in a 16-bit audio ΣΔ ADC architecture.© (2005) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Integration technologies have favored the design and implementation of more complex circuits. Thanks to this increased complexity, these circuits are capable of implementing algorithms which a few years ago were too expensive in both area and computational resources. However, they now offer interesting choices which should be considered. This new generation of integrated circuits nevertheless presents other kinds of restrictions that the designer should bear in mind. Parameters such as frequency of operation or power consumption are new restrictions that the designer has to deal with in order to fulfill the conditions established by the circuit functionality. Finally, the shrinking integration scale of current technologies makes the timing behavior of the design differ from previous technologies. Thus, a review of the timing behavior of the digital circuit should be done. So far, arithmetic circuits have been used as a benchmark for the analysis and design procedures of digital circuits. Therefore, it is our goal now to analyze both conventional and modern arithmetic circuits structures for different deep-submicron technologies. To achieve this goal, a good solution is to characterize a set of algorithmic circuits for several deep submicron processes, so that the designer can select the most suitable one depending upon the intended application and existing restrictions. In this paper, the first steps to attain such selection are presented. In particular, we propose a design and VHDL characterization methodology based on an RTL description of each component, on the utilization of an automated synthesis tool, and on the generation of logic characteristics from the logic level. This methodology is applied to a set of adders structures, the results of which are also presented.

In this paper we present a contribution to create a VHDL-AMS radio-frequency component library. Currently, integrated circuit technology tends to integrate in a sole chip not only mixed signal but also mixed technology systems, going to a more general definition of the so called Systems On Chip. A library of RF models would be useful to model, in a same framework, circuits and systems of different physical domains, including RF, which will certainly optimise design process of such systems. Generally, VHDL-AMS, the analogue and mixed signal extension to IEEE standard VHDL does not include specific formulation for RF devices or systems modeling, as it does not support distributed parameters for simulation or description purposes. However, RF devices can be modeled by means of more general VHDL-AMS resources, like sentences including algebraic and trigonometric relations.

In this paper a modified relaxation oscillator is proposed as the core of an analog to digital modulator for on chip signal extraction for test. The architecture uses digital current source generation and digital switching in place of active circuitry. The resulting design allows for high input sensitivity, robustness to component variation while occupying little silicon area. This paper provides solutions on the main challenges in implementing this modulator and how it may be integrated with a digital based tester.

This paper presents a toolbox for the simulation, optimization and high-level synthesis of Nyquist-rate Analog-to-Digital (A/D) and Digital-to-Analog (D/A) Converters in MATLAB. The embedded simulator uses SIMULINK C-coded S-functions to model all required subcircuits including their main error mechanisms. This approach allows to drastically speed up the simulation CPU-time up to 2 orders of magnitude as compared with previous approaches - based on the use of SIMULINK elementary blocks. Moreover, S-functions are more suitable for implementing a more detailed description of the circuit. For all subcircuits, the accuracy of the behavioral models has been verified by electrical simulation using HSPICE. For synthesis purposes, the simulator is used for performance evaluation and combined with an hybrid optimizer for design parameter selection. The optimizer combines adaptive statistical optimization algorithm inspired in simulated annealing with a design-oriented formulation of the cost function. It has been integrated in the MATLAB/SIMULINK platform by using the MATLAB engine library, so that the optimization core runs in background while MATLAB acts as a computation engine. The implementation on the MATLAB platform brings numerous advantages in terms of signal processing, high flexibility for tool expansion and simulation with other electronic subsystems. Additionally, the presented toolbox comprises a friendly graphical user interface to allow the designer to browse through all steps of the simulation, synthesis and post-processing of results. In order to illustrate the capabilities of the toolbox, a 0.13μm CMOS 12-bit@80MS/s analog front-end for broadband power line communications, made up of a pipeline ADC and a current steering DAC, is synthesized and high-level sized. Different experiments show the effectiveness of the proposed methodology.

Despite the spectacular breakthroughs of the semiconductor industry, the ability to design integrated circuits (ICs) under stringent time-to-market (TTM) requirements is lagging behind integration capacity, so far keeping pace with still valid Moore"s Law. The resulting gap is threatening with slowing down such a phenomenal growth. The design community believes that it is only by means of powerful CAD tools and design methodologies - and, possibly, a design paradigm shift - that this design gap can be bridged. In this sense, reuse-based design is seen as a promising solution, and concepts such as IP Block, Virtual Component , and Design Reuse have become commonplace thanks to the significant advances in the digital arena. Unfortunately, the very nature of analog and mixed-signal (AMS) design has hindered a similar level of consensus and development. This paper presents a framework for the reuse-based design of AMS circuits. The framework is founded on three key elements: (1) a CAD-supported hierarchical design flow that facilitates the incorporation of AMS reusable blocks, reduces the overall design time, and expedites the management of increasing AMS design complexity; (2) a complete, clear definition of the AMS reusable block, structured into three separate facets or views: the behavioral, structural, and layout facets, the two first for top-down electrical synthesis and bottom-up verification, the latter used during bottom-up physical synthesis; (3) the design for reusability set of tools, methods, and guidelines that, relying on intensive parameterization as well as on design knowledge capture and encapsulation, allows to produce fully reusable AMS blocks. A case study and a functional silicon prototype demonstrate the validity of the paper"s proposals.© (2005) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

By 2006, close to 75% of system on a chip (SOC) designs will be mixed-signal in nature with digital, analog and possibly RF circuitry all integrated on a single chip. This paper will cover recommended design flows and the design methodology challenges facing current mixed signal SOC designers. It also addresses the CAD tool interoperability issues for these types of mixed-signal designs and identifies the work and solution that need to be done to enable their fast design turnaround.

This paper presents an approach for the analysis and the experimental evaluation of crosstalk effects due to current pulses drawn from voltage supplies in mixed analog-digital CMOS integrated circuits. A realistic model of bonding and package parasitics has been derived to study digital switching noise injected through bonding interconnections. Simulations results indicate that disturbances due to switching currents in digital blocks propagate through the substrate and affect analog voltages, thus degrading circuit performance. Test structures have been integrated into a test chip mounted with different technologies, in order to compare the measurements on test chips. Measurements confirm simulation results. Chip-on-board mounting technology has better performance with respect to chip-in-package, due to the reduction of parasitic elements.

Address Event Representation (AER) is an emergent neuromorphic interchip communication protocol that allows for real-time virtual massive connectivity between huge number of neurons located on different chips. By exploiting high speed digital communication circuits (with nano-seconds timings), synaptic neural connections can be time multiplexed, while neural activity signals (with mili-seconds timings) are sampled at low frequencies. Also, neurons generate events according to their information levels. Neurons with more information (activity, derivative of activities, contrast, motion, edges,...) generate more events per unit time, and access the interchip communication channel more frequently, while neurons with low activity consume less communication bandwidth. AER technology has been used and reported for the implementation of various type of image sensors or retinae: luminance with local agc, contrast retinae, motion retinae,... Also, there has been a proposal for realizing programmable kernel image convolution chips. Such convolution chips would contain an array of pixels that perform weighted addition of events. Once a pixel has added sufficient event contributions to reach a fixed threshold, the pixel fires an event, which is then routed out of the chip for further processing. Such convolution chips have been proposed to be implemented using pulsed current mode mixed analog and digital circuit techniques. In this paper we present a fully digital pixel implementation to perform the weighted additions and fire the events. This way, for a given technology, there is a fully digital implementation reference against which compare the mixed signal implementations. We have designed, implemented and tested a fully digital AER convolution pixel. This pixel will be used to implement a full AER convolution chip for programmable kernel image convolution processing.

Over the years, Field Programmable Gate Arrays (FPGAs) have made a profound impact on the electronics industry with rapidly improving semiconductor-manufacturing technology ranging from sub-micron to deep sub-micron processes and equally innovative CAD tools. Though FPGA has revolutionized programmable/reconfigurable digital logic technology, one limitation of current FPGA’s is that the user is limited to strictly electronic designs. Thus, they are not suitable for applications that are not purely electronic, such as optical communications, photonic information processing systems and other multi-technology applications (ex. analog devices, MEMS devices and microwave components). Over recent years, the growing trend has been towards the incorporation of non-traditional device technologies into traditional CMOS VLSI systems. The integration of these technologies requires a new kind of FPGA that can merge conventional FPGA technology with photonic and other multi-technology devices. The proposed new class of field programmable device will extend the flexibility, rapid prototyping and reusability benefits associated with conventional electronic into photonic and multi-technology domain and give rise to the development of a wider class of programmable and embedded integrated systems. This new technology will create a tremendous opportunity for applying the conventional programmable/reconfigurable hardware concepts in other disciplines like photonic information processing. To substantiate this novel architectural concept, we have fabricated proof-of-the-concept CMOS VLSI Multi-technology FPGA (MT-FPGA) chips that include both digital field programmable logic blocks and threshold programmable photoreceivers which are suitable for sensing optical signals. Results from these chips strongly support the feasibility of this new optoelectronic device concept.

We analyze the optoelectronic mixing characteristics of InAlAs, Schottky-enhanced, InGaAs-based, metal-semiconductor-metal photodetectors. For devices with Schottky-enhancement layers (SELs) of about 500 a, the measured frequency bandwidth is less than that of a corresponding photodetector. The mixing efficiency decreases with decrease in optical power, decreases with increase in local oscillator frequency and decreases with decrease in mixed signal frequency. We attribute this behavior to the band-gap discontinuity associated with the SEL. For devices with thinner SELs (≈100 a), the mixing characteristics are greatly improved: the bandwidth of the optoelectronic mixer (OEM) is similar to that of a corresponding photodetector and the mixing efficiency decreases only slightly with decrease in optical power. We attribute these results to the enhancement of the thermionic/tunneling current through the thinner SEL. We also present a circuit model of the Schottky-enhanced, InGaAs-based OEM to explain the experimental results.