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Since the early 2000s, silicon nanowire field effect transistors are emerging as ultrasensitive biosensors while offering label-free, portable and rapid detection. Nevertheless, their large scale production remains an ongoing challenge due to time consuming, complex and costly technology. In order to bypass these issues, we report here on the first integration of silicon nanowire networks, called nanonet, into long channel field effect transistors using standard microelectronic process. A special attention is paid to the silicidation of the contacts which involved a large number of SiNWs. The electrical characteristics of these FETs constituted by randomly oriented silicon nanowires are also studied. Compatible integration on the back-end of CMOS readout and promising electrical performances open new opportunities for sensing applications. [ABSTRACT FROM AUTHOR]

We studied the current-voltage characteristics of percolating networks of silicon nanowires (nanonets), operated in back-gated transistor mode, for future use as gas or biosensors. These devices featured P-type field-effect characteristics. It was found that a Lambert W function-based compact model could be used for parameter extraction of electrical parameters such as apparent low field mobility, threshold voltage and subthreshold slope ideality factor. Their variation with channel length and nanowire density was related to the change of conduction regime from direct source/drain connection by parallel nanowires to percolating channels. Experimental results could be related in part to an influence of the threshold voltage dispersion of individual nanowires. [ABSTRACT FROM AUTHOR]

Mechanical stress is an established and important tool of the semiconductor industry to improve the performance of modern transistors. It is well understood for the enhancement of carrier mobility but rather unexplored for the control of the tunneling probability for injection dominated research devices based on tunneling phenomena, such as tunnel FETs, resonant tunnel FETs and reconfigurable Schottky FETs. In this work, the effect of stress on the tunneling probability and overall transistor characteristics is studied by three-dimensional device simulations in the example of reconfigurable silicon nanowire Schottky barrier transistors using two independently gated Schottky junctions. To this end, four different stress sources are investigated. The effects of mechanical stress on the average effective tunneling mass and on the multi-valley band structure applying the deformation potential theory are being considered. The transfer characteristics of strained transistors in n- and p-configuration and corresponding charge carrier tunneling are analyzed with respect to the current ratio between electron and hole conduction. For the implementation of these devices into complementary circuits, the mandatory current ratio of unity can be achieved by appropriate mechanical stress either by nanowire oxidation or the application of a stressed top layer. [ABSTRACT FROM AUTHOR]

The highly sensitive operation of a bottom-gate silicon nanowire (SiNW) field-effect transistor (FET)-based hydrogen (H 2 ) sensor is demonstrated by controlling the working regime of the sensor. It is observed that the deposition of palladium (Pd) nanoparticles on the SiNW surface for the selective absorption of H 2 can result in a significant enhancement of the electrostatic properties, such as the subthreshold swing and on-current, of the SiNW FET-based H 2 sensor. By comparing the experimental results with the numerical simulation, we conclude that the improvement of the electrostatic properties of the sensor is due to the coupling effect between the electrostatic potentials in the Pd nanoparticle and bottom gate. Based on these results, highly sensitive detection of H 2 gas could be achieved in the subthreshold regime where the gating effect induced by absorbed H 2 gas is the most effective. [ABSTRACT FROM AUTHOR]

Abstract: The sp3d5s∗-spin–orbit-coupled atomistic tight-binding (TB) model is used for the electronic structure calculation of Si nanowires (NWs), self consistently coupled to a 2D Poisson equation, solved in the cross section of the NW. Upon convergence, the linearized Boltzmann transport theory is employed for the mobility calculation, including carrier scattering by phonons and surface roughness. As the channel is driven into inversion, for [111] and [110] NW devices of diameters D >10nm the curvature of the bandstructure increases and the hole effective mass becomes lighter, resulting in a ∼50% mobility increase. Such improvement is large enough to compensate for the detrimental effect of surface roughness scattering. The effect is very similar to the bandstructure variations and mobility improvement observed under geometric confinement, however, in this case confinement is caused by electrostatic gating. We provide explanations for this behavior based on features of the heavy-hole band. This effect could be exploited in the design of p-type NW transistor devices. We note, finally, that the “apparent” mobility of low dimensional short channel transistors is always lower than the intrinsic channel diffusive mobility due to the detrimental influence of the so called “ballistic” mobility. [Copyright &y& Elsevier]

Abstract: In this paper we show that on scaling nanowire width from 20nm down to sub-7nm regime, together with achieving excellent short channel effect control (DIBL=12mV/V for L G =20nm), we hit a dramatic transition in transport mechanism from monotonously increasing I D–V G of a FET to oscillating I D–V G of a Single Electron Transistor. This transition in transport mechanism is brought about by process induced channel potential variability. It poses a challenge to further scaling of nanowire MOSFETs. However, we show that it provides an exciting opportunity to cointegrate Single Electron Transistors with high-k/metal gate operating at room temperature (at V D =±0.9V) with the state-of-the-art nanowire MOSFETs enabling large scale manufacturing of Beyond Moore devices. [Copyright &y& Elsevier]

Abstract: In this paper, we address a physics based closed form model for the energy band gap (E g ) and the transport electron effective mass in relaxed and strained [100] and [110] oriented rectangular Silicon Nanowire (SiNW). Our proposed analytical model along [100] and [110] directions are based on the k.p formalism of the conduction band energy dispersion relation through an appropriate rotation of the Hamiltonian of the electrons in the bulk crystal along [001] direction followed by the inclusion of a 4×4 Lüttinger Hamiltonian for the description of the valance band structure. Using this, we demonstrate the variation in E g and the transport electron effective mass as function of the cross-sectional dimensions in a relaxed [100] and [110] oriented SiNW. The behaviour of these two parameters in [100] oriented SiNW has further been studied with the inclusion of a uniaxial strain along the transport direction and a biaxial strain, which is assumed to be decomposed from a hydrostatic deformation along [001] with the former one. In addition, the energy band gap and the effective mass of a strained [110] oriented SiNW has also been formulated. Using this, we compare our analytical model with that of the extracted data using the nearest neighbour empirical tight binding sp3d5s∗ method based simulations and has been found to agree well over a wide range of device dimensions and applied strain. [Copyright &y& Elsevier]

Abstract: Gate length (LG ) effects for program/erase (P/E) efficiency are investigated in a gate-all-around (GAA) SONOS structure. The experimental results show that P/E characteristics become worse at a shorter LG , and this trend is verified with numerical simulation. The down-scaling of LG gives rise to a change in the electric field in tunneling oxide and blocking oxide in the GAA–SONOS structure. For P/E efficiency, these results reveal that the fringing field via a low-k dielectric medium, which encapsulates a gate electrode as an inter-layer dielectric, favorably enhances the electric field of tunneling oxide. It also reduces the electric field of blocking oxide. Additionally, it is found that the electric field of tunneling and blocking oxide becomes more sensitive to the permittivity of the inter-layer dielectric as LG is more shortened. [Copyright &y& Elsevier]

Abstract: In this paper we report on a newly developed nanowire based field-effect device-architecture feasible for the use in high temperature environments. This nanowire field-effect-transistor (NWFET) is virtually undoped and therefore the device type (i.e. P-type or N-type) can be selected by the application of an appropriate bias to a second gate, namely the back-gate, enabling an additional degree of freedom in logic design. Moreover, the presented devices exhibit low OFF-state currents, even at elevated temperatures, making low-power applications attainable with today’s conventional silicon (and SOI) CMOS technology. By changing the source/drain bias-polarity, electrical properties of the NW-devices can be tuned, whether the lowest possible leakage current, or maximum output current is desirable in a specific logic application. [Copyright &y& Elsevier]

Abstract: We calculate the transport characteristics of thin silicon nanowires (NWs) up to 12nm in diameter. The sp3d5s*-spin–orbit–coupled atomistic tight-binding (TB) model is used for the electronic structure calculation. Linearized Boltzmann transport theory is applied for transport, including carrier scattering by phonons and surface roughness (SRS). We show that for certain transport orientations, confinement in specific directions enhances the curvature of the subbands such that large improvements can be achieved in carrier velocity and mobility. This is observed for p-type [110] and [111] NWs for which confinement-induced bandstructure changes improve the phonon limited mobility by >2X compared to bulk values. Such improvement suggests very large carrier mean-free-paths for scattering and is large enough to compensate for the detrimental effect of SRS. This effect is observed at a smaller degree for n-type [110] NWs as well. The bandstructure engineering techniques we describe originate from the warped, anisotropic bulk bands, and can be also applied to 2D ultra-thin-body (UTB) layers as well as other channel materials. Our results may provide understanding of recent experimental observations, as well as guidance in the design of NW and UTB channel devices with improved transport properties. [Copyright &y& Elsevier]

Abstract: In this paper, we report on the fabrication and characterization of voltage configurable nanowire field-effect-transistor (NWFET) devices suitable to broaden the flexibility in circuit design, e.g. for reconfigurable logic. Silicon NW-structures with mid-gap Schottky source and drain (S/D) junctions on silicon-on-insulator (SOI) substrate have been fabricated as unipolar complementary metal–oxide–semiconductor (CMOS) transistors. The desired device type, i.e. NMOS or PMOS, is selected by applying an appropriate back-gate bias. The programming capabilities of the devices fabricated using this approach are demonstrated experimentally using a freely configurable CMOS-NWFET inverter circuit on a MultiSOI-substrate like set-up. [Copyright &y& Elsevier]

Abstract: Structural effects, especially corner angle of upper-corners of trapezoidal and rectangular, and triangular cross-sectional shapes of silicon nanowire field-effect transistors on effective carrier mobility and normalized inversion charge density have been investigated. 〈100〉-directed silicon nanowire field-effect transistors with semi-gate around structure fabricated on (100)-oriented silicon-on-insulator wafers were evaluated. As the upper-corner angle decreased from obtuse to acute angle, we observed an increased amount of inversion charge using split-CV measurement. On the other hand, the effective carrier mobility dependence on the upper-corner angle seems to have an optimized point near 100° at 296K. Although normalized inversion charge density was the largest with acute angles, effective carrier mobility with acute upper-corner angle was severely degraded. Considering the intrinsic delay time of SiNW FET, SiNW FETs with trapezoidal cross-section with upper-corner angle of 100° is more suitable in this work to achieve high electrical performance. We believe these findings could represent guidelines for the design of high-performance SiNW FETs. [Copyright &y& Elsevier]

Abstract: Electronic characteristics of silicide/silicon interface were studied in the suspended, chemically synthesized silicon nanowires (SiNWs). Step-by-step intrusion of a silicide/Si interface along the axial direction of a suspended silicon nanowire was performed by repeated thermal annealing cycles, and the current–voltage (I–V) characteristics of the annealed silicide/SiNW/silicide structure were measured at each cycle. The intruded length of the silicide was found to be directly proportional to the total annealing time, but the rate of silicidation was much smaller than previous works on similar silicide/SiNWs. A structural kink with Ni atoms diffused along the sidewall created a secondary source of silicidation, resulting in anomalous I–V characteristics. The measured I–V including this unintentional silicidation in the Si channel was explained by various combinations of Schottky barriers and resistors. [ABSTRACT FROM AUTHOR]

Abstract: In this work a quasi-analytical physical model has been developed for the prediction of the potential in SiNW devices with arbitrary polygonal cross section. The model is then extended to the transport direction; a method for the calculation of the natural channel length has been proposed and validated by means of 2D and 3D numerical device simulations. With the results based on the proposed model it is possible to compare nanowires with cross sections of different shape and predict the minimum technological gate length able to assure immunity to the SCEs. [Copyright &y& Elsevier]

Abstract: Silicon nanowire (Si NW) field-effect transistors with a semi gate-around structure suitable for integration have been fabricated using conventional CMOS processes. With the use of SiO2 pedestal and SiN sidewall, lithography and etching steps over NW can easily realized. A subthreshold slope (SS) of 71mV/dec. with I ON/I OFF >105 and a high on-current of 49.6μA at V g–V th =1.0V have been obtained with a 25-nm-wide Si NW FET with a gate length and oxide thickness of 200 and 5nm, respectively. Normalization of the on-current by peripheral length of Si NW FET from 25 to 45nm in width has revealed comparable current density, which suggests that carriers are formed at the periphery of NW. The effective electron mobility of Si NW FETs has been revealed to be comparable to that of planar FET, indicating negligible process induced damages. The proposed process has a high potential for Si NW FET for large scale integration. [Copyright &y& Elsevier]

Abstract: Silicon nanowire transistors are measured at low temperature in the Coulomb blockade regime. Coulomb blockade spectroscopy permits to determine the gate, source and drain capacitances. We propose a model to explain the origin of both the gate and source (drain) capacitances for quantum dots formed in gated silicon nanowires. The gate capacitance is found to be determined by the gate-wire overlap capacitor and does not depend on gate voltage. On the contrary, the source (drain) capacitances increase with gate voltage. This feature is related to the increase of the electronic polarizability in the access regions. [Copyright &y& Elsevier]

Abstract: This work investigates the conduction band structure of silicon nanowires, its dependence with the wire width and its influences on the electrical performances of Si nanowire-based MOSFET’s working in the ballistic regime. The energy dispersions relations for Si nanowires have been calculated using a sp3 tight-binding model and the ballistic response of n-channel devices with a 3D Poisson–Schrödinger solver considering a mode-space approach and open boundary conditions (NEGF formalism). Results are compared with data obtained considering the parabolic bulk effective mass approximation, highlighting in this last case the overestimation of the I on current, up to 60% for the smallest (1.36nm×1.36nm Si wire) devices. [Copyright &y& Elsevier]

Abstract: In this work we investigate and compare the electrostatics of fully depleted cylindrical silicon-nanowire (SiCNW) FETs, four-gate rectangular nanowire (4G RNW) FETs, tri-gate rectangular nanowire (3G RNW) FETs and gate-all-around carbon-nanotube (GAA-CNT) FETs at advanced miniaturization limits. In doing so, we rigorously solve the coupled Schrödinger–Poisson equations within the device cross-sections and fully account for quantum-mechanical effects. The investigation, carried out for the 65 and 45nm technology nodes, leads to the unexpected conclusion that, for an assigned threshold voltage, the gate-all-around CNT-FET offers only a slightly better performance with respect to the SiCNW and the 4G RNW-FETs. This is due to the compensation of two different mechanisms, namely a higher gate effectiveness and a lower density of states. The 3G RNW yields instead an electron density within the channel which is about 25% lower than the SiCNW and 4G RNW-FETs at a given gate voltage. Such a reduced performance is due to its inherent asymmetry, which negatively affects the gate control on the channel charge. [Copyright &y& Elsevier]

In this paper, we compare the evolution with temperature of the experimental characteristics of Nanonet-based Field-Effect Transistors, with a modelling of carrier transport in the percolating regime. The main electrical parameters of Nanonet-based Field-Effect Transistors that featured different nanowire densities and source-drain distances were extracted from static measurements at different temperatures. The temperature dependence of low field mobility and threshold voltage was explained by the temperature activated behaviour of inter-nanowire junctions, and the activation energy dispersion of individual junctions. A Monte-Carlo simulation of Nanonet FET in the shape of a random percolating network of resistances and thermally activated junctions was used to confirm the influence of activation energy dispersion on low field mobility. The simplest model which was able to capture experimental trends consisted in a bimodal distribution of activation energies, with a subset of non-thermally activated junctions (resistive junctions) while other junctions were thermally activated (energy barriers at the junctions). [ABSTRACT FROM AUTHOR]