Search

Crossbar architecture has been considered as an efficient means to execute a matrix-vector multiplication computation. An efficient evaluation model for this computation including the interconnect resistance effect on the high density resistive random access memmory (RRAM) crossbar array is proposed in this paper. The proposed model considers the interconnect resistance impacts on the columns and rows separately. The simulation results indicate that the computing speed of the proposed model can be boosted by over three orders of magnitude with the computation deviation of 7.7% in comparison with the precise comprehensive model in the 64 kb crossbar array fabricated at the 14 nm technology node. Based on the proposed evaluation model, the impacts of the parameters including nonlinearity and load resistance, on the computation are discussed along with solutions to improve the computational performance.

本文利用潜通路电流作为故障表征, 提出针对1TnR结构的阻变存储器(RRAM)阵列测试方法。在提出一种基于潜通路的1TnR RRAM阵列测试读操作的基础上, 设计了一种新的1TnR RRAM测试算法, 可以较低的测试算法复杂度代价, 达到高故障覆盖率, 优于现有RRAM阵列测试算法。该算法对于阻值波动具有一定容忍能力, 适用于偏平型1TnR RRAM阵列的测试。

Differential fault analysis (DFA) aiming at the advanced encryption standard (AES) hardware implementations has become a widely research topic. Unlike theoretical model, in real attack scenarios, popular and practical fault injection methods like supply voltage variation will introduce faults with random locations, unknown values and multibyte. For analyzing this kind of faults, the previous fault model needed six pairs of correct and faulty ciphertexts to recover the secret round-key. In this paper, on the premise of accuracy, a more efficient DFA attack with unknown and random faults is proposed. We introduce the concept of theoretical candidate number in the fault analysis. Based on this concept, the correct round-key can be identified in advance, so the proposed attack method can always use the least pairs of correct and faulty ciphertexts to accomplish the DFA attacks. To further support our opinion, random fault attacks based on voltage violation were taken on an FPGA board. Experiment results showed that about 97.3% of the attacks can be completed within 3 pairs of correct and faulty ciphertexts. Moreover, on average only 2.17 pairs of correct and faulty ciphertexts were needed to find out the correct round-key, showing significant advantage of efficiency compared with previous fault models. On the other hand, less amount of computation in the analyses can be realized with a high probability with our model, which also effectively improves the time efficiency in DFA attacks with unknown and random faults.

Phase change memory (PCM) is one of the most promising candidates for next generation nonvolatile memory. However, PCM suffers from a variety of faults due to its special device structure and operation mechanism. A snake addressing scheme is introduced into the test algorithms of PCM to reduce the test time and excite proximity disturb faults more effectively. The March test algorithm with the proposed snake addressing scheme is less complex than most traditional test algorithms. In addition to conventional faults, it is capable of covering disturb and parasitic faults. Moreover, when incorporated with the sneak path testing method, it is able to test the read fault, read recovery fault, incomplete program fault 0, and false write fault.

In this paper, we first reconstruct a novel planar static contention-free single-phase-clocked flip-flop (S$^{2}$CFF) based on high-performance fin-type field-effect transistors (FinFETs) to achieve high speed and ultralow power consumption. Benefiting from better control of the conductive channel, the shorted-gate (SG-mode) FinFET flip-flop obtains a persistent reduction of 56.7% in average power consumption as well as a considerable improvement in timing performance at a typical 10% data switching activity, while the low-power (LP-mode) FinFET flip-flop promotes the power reduction to 61.8% without appreciable degradation in speed. However, through further analysis of the simulation results, we have revealed an unnecessary energy loss caused by the redundant leaps of internal nodes at the static input `0, which has a noticeable negative impact on total power consumption at low data switching activity. In order to overcome this defect, a conditional precharge technique is introduced to control the charging path, and we demonstrate that the independent-gate (IG-mode) FinFET is the best option for the added control transistor. The verification results indicate that our optimization reduces the power consumption by more than 50% at low data switching activity with an acceptable area and setup time penalty compared with that of LP-mode FinFET flip-flop.