Ultralow-power high-speed flip-flop based on multimode FinFETs

In this paper, we first reconstruct a novel planar static contention-free single-phase-clocked flip-flop (S$^{2}$CFF) based on high-performance fin-type field-effect transistors (FinFETs) to achieve high speed and ultralow power consumption. Benefiting from better control of the conductive channel, the shorted-gate (SG-mode) FinFET flip-flop obtains a persistent reduction of 56.7% in average power consumption as well as a considerable improvement in timing performance at a typical 10% data switching activity, while the low-power (LP-mode) FinFET flip-flop promotes the power reduction to 61.8% without appreciable degradation in speed. However, through further analysis of the simulation results, we have revealed an unnecessary energy loss caused by the redundant leaps of internal nodes at the static input `0, which has a noticeable negative impact on total power consumption at low data switching activity. In order to overcome this defect, a conditional precharge technique is introduced to control the charging path, and we demonstrate that the independent-gate (IG-mode) FinFET is the best option for the added control transistor. The verification results indicate that our optimization reduces the power consumption by more than 50% at low data switching activity with an acceptable area and setup time penalty compared with that of LP-mode FinFET flip-flop.