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In this article, we review the recent progress on GaAs MOSFET's using in-situ MBE-grown Ga2O3(Gd2O3) as the gate dielectric. Both depletion-mode (D-mode) and inversion-mode (I-mode) GaAs MOSFET's with negligible drain current drift and hysteresis are demostrated. The absence of drain current drift and hysteresis indicates that the excellent stability of the oxide and low oxide/GaAs interface state density have been achieved. The drain current density and transconductance are about one order of magnitude higher than the best previous reported data in the literature for an inversion-mode GaAs MOSFET. Excellent high frequency and power performances were also measured from the depletion-mode devices. These improvements are attributed to the excellent Ga2O3(Ga2O3) oxide properties and novel processing techniques.

We demonstrate a vacuum lithography process which uses a finely focused Ga ion beam to write the pattern which is then transferred to the InP pattern by low energy dry etching. Surface steps on the order of 1000-2000A in height, and lateral resolution limited only by size of the ion beam, can be efficiently prepared using moderate Ga ion fluences. The surfaces prepared by this process are damage free and suitable for epitaxial overgrowth. GaInAs/InP heterostructures grown on in-situ patterned substrates show excellent morphology and high luminescence efficiency.

Recent progress of GaAs-on-Si technology is reviewed and the importance of initial nucleation is emphasized. Growth initiation with a Ga prelayer at a suitable low temperature combined with migration enhanced epitaxy and in-situ thermal annealing has a prospect of giving substantially improved material quality. During the initial growth, use of the minimum necessary As4/Ga flux ratio is found to be critical. The random alignment of the major axis of the oval defects is suggested to be an alternative simple technique to detect the presence of antiphase domains. Patterned growth or post growth patterning releases tensile stress only if the growth edges are free. GaAs-on-Si was completely relaxed from stress by post-growth patterning to 5 μm × 5 μm size patterns. Steps on the surface due to substrate misorientation do not affect the two dimensional electron gas (2DEG) transport properties in AlGaAs/GaAs selectively doped heterojunction transistor (SDHT) structures. For a sheet density of 1012 cm−2, the 2DEG mobility >50,000 cm2V−1s−1 at 77 K was obtained on Si substrates, which is sufficient for fabrication of high performance SDHTs. The study shows that GaAs-on-Si has a great potential for SDHT technology.

In optical experiments with laterally patterned modulation-doped GaAs/AlGaAs quantum wells we observe spatially separate confinement of electrons and holes to one-dimensional quantum wires. We determine the one-dimensional subband spacing and Fermi energy from inelastic light scattering and photoluminescence spectra. From these measurements we directly determine the one-dimensional electron density.

The biaxial tensile stress of 2.65 kbar in as-grown GaAs/Si for T < 100K is reduced by post-growth patterning of the GaAs and the reduction in stress, as determined by photoluminescence and cathodoluminescence, is dependent on the pattern size and shape. For stripe patterns less than 15 gm wide the stress is largely uniaxial with stress relief normal to the stripe direction. Rectangular patterns exhibited stress relief in orthogonal directions, and a 9 x 12 µm2 rectangle exhibited an average stress of 0.5 kbar. For as-grown GaAs/Si layers 0.9 to 3.25 µm thick, the stress is weakly dependent on layer thickness. For T > looK the stress in as-grown GaAs/Si is reduced and at 295K a value of 1.51 ± 0.21 kbar is obtained. With patterned growth, using a native SiO2 mask, no reduction in stress was observed irrespective of the pattern size, indicating the importance of free GaAs edges in obtaining stress relief.