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A 3.5 GHz low insertion loss variation phase shifter has been designed and fabricated on standard 0.18‐μm CMOS process. To achieve over 360° continuously phase tuning range, the phase shifter consists of a switch type phase shifter (STPS) and a reflection type phase shifter (RTPS). The phase‐invertible variable attenuator (PIVA) topology which can provide two states with 180° phase‐shift while maintaining low amplitude imbalance is adopted. The RTPS provides over 189° continuously phase tuning. The experimental results show that the 3.5 GHz phase shifter demonstrates over 360° continuously phase tuning range with low insertion loss variation of 1 dB at 3.5 GHz. The maximum insertion loss is 13.5 dB at 3.5 GHz and the dc consumption is zero. The chip size is 1.08 mm × 0.82 mm. [ABSTRACT FROM AUTHOR]

Abstract: In this letter, a dual‐band class‐E CMOS power amplifier (PA) in 0.18‐μm CMOS process is presented. By using concurrent dual‐band impedance matching network, the proposed dual‐band PA can achieve high efficiency in a compact chip area. This dual‐band class‐E PA demonstrates the power gain ≥ 8.4 dB, Psat ≥ 21.4 dBm with power added efficiency ≥ 31% in a compact chip size of 0.5 mm2. This dual‐band class‐E PA achieves comparable power area density of 284.5 (mW/mm2) with other state‐of‐the‐art class‐E PAs at higher frequency. [ABSTRACT FROM AUTHOR]

A 224-448 MHz low-power fully integrated phase-locked loop (PLL) is designed and implemented in standard 0.18-μm CMOS process. For wide tuning rage and compact circuit size, a differential ring-type voltage-controlled oscillator (VCO) is adopted. The replica bias circuit is added to provide the required voltage for the delay cell of the VCO. For low dc consumption, a high-speed true single phase clock (TSPC) divider is used. The PLL achieves wide operating frequency from 224 to 448 MHz with low dc power consumption of 2.62 mW from 1.8 V voltage supply. The measured phase noises are −98 and −115 dBc/Hz at 100 kHz and 10 MHz frequency offsets, respectively. [ABSTRACT FROM AUTHOR]

ABSTRACT This article presents a wideband phase-locked loop (PLL) front-end, which consists of a dual-core voltage-controlled oscillator (VCO) and a divide-by-four (D4) frequency divider in 90-nm CMOS technology. The switched inductors and varactor banks are used to enhance the tuning range of VCO. The D4 frequency divider is a body-biased injection-locked frequency divider (ILFD) cascoded with source-injection current mode logic (SICML) for wider locking range and lower power consumption. This PLL front-end demonstrates a 30.2% frequency tuning range (FTR) from 23.6 to 32 GHz and a phase noise of −101.22 dBc/Hz at 5.86 GHz with 1 MHz offset frequency. The output power is higher than −15 dBm among the operating bandwidth. The dc power consumption is 40.8 mW at 1.2 V and 1.5 V supply voltages. © 2017 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:1305-1309, 2017 [ABSTRACT FROM AUTHOR]

ABSTRACT A K-band differential cross-coupled inductance- capacitance (LC) voltage-controlled oscillator (VCO) is implemented in 0.18-μm CMOS process. To accomplish high quality (Q) factor LC-tank at K-band, a slab inductor with high Q is adopted. The VCO can be tuned from 23.1 to 23.38 GHz and the core dc power consumption is 11.33 mW from 1 V power supply. The phase noise is −109.04 dBc/Hz at 1 MHz offset, and the calculated figure of merit (FoM) is −185.79 dBc/Hz. At low supply voltage mode of 0.65 V, the phase noise is −106.015 dBc/Hz at 1 MHz offset and the FoM is −189.76 dBc/Hz. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:362-366, 2017 [ABSTRACT FROM AUTHOR]

ABSTRACT A 5 GHz fully integrated low-power phase-locked loop (PLL) was designed and fabricated on 0.18-μm CMOS process. To achieve low power consumption, the transformer feedback VCO and high speed true single phase clock (TSPC) divider were adopted. A rail-to-rail buffer amplifier was incorporated between the VCO and TSPC divider chain to provide full voltage swing for TSPC input. In addition, dual varactor pairs were utilized to enlarge the tuning rage of the VCO while maintaining the low KVCO. The PLL achieved low power of 12.12 mW with good phase noise. The closed loop phase noises were −90.88 and −115.8 dBc/Hz at 100 kHz and 10 MHz frequency offsets. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:1534-1537, 2016 [ABSTRACT FROM AUTHOR]

ABSTRACT A Ku-band 3-bit switch-type phase shifter with low insertion loss, low magnitude variation, and low rms phase error is designed and fabricated on 0.15-μm pHEMT process. For all eight states, the insertion loss is 6.5 ± 1.5 dB from 10-14 GHz and the input return loss is >8.5 dB over 10-14 GHz. The phase shifter achieves a rms phase error of 2.2° and a rms amplitude error of 0.37 dB at 12 GHz with total chip size of 1.5 ×1 mm2. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:771-774, 2015 [ABSTRACT FROM AUTHOR]

ABSTRACT In this letter, a 6-GHz spread spectrum clock generation for Serial AT Attachment Generation 3 (SATA-III) applications in 0.18-pm CMOS technology is presented. The 3rd-order loop filter is to reduce the ripple of control voltage of VCO and the loop bandwidth is 625 KHz. With the aid of second-order delta-sigma (ΔΣ) modulator and triangular profile counter, the division ratio of divider chain can be changed periodically. The modulation frequency is 37.04 KHz with upper bound of 19 for the triangular profile counter. The proposed circuit spreads 30-MHz frequency range from 5.97 to 6.0 GHz with an EMI reduction of 20.3 dB. The dc power consumption is 34 mW with a chip size of 0.54 mm2. © 2017 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:622-624, 2017 [ABSTRACT FROM AUTHOR]

ABSTRACT A V-band variable gain amplifier (VGA) with wide gain control range, low phase variation, and low return loss variation is designed and implemented on 90-nm CMOS process. Utilizing a phase compensation capacitor at the common gate transistor and a source degeneration inductor at the common source transistor of the cascode configuration, the VGA achieves gain control range of 15.8 dB with only 6.9° transmission phase variation at 60 GHz via simple control mechanism. The maximum small signal gain is 15.8 dB at 60 GHz. In addition, the input/output return losses are insensitivity at different gain state of the VGA. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:1946-1949, 2014 [ABSTRACT FROM AUTHOR]

A DC-20-GHz broadband and compact single-pole-quadruple-throw (SPQT) switch for Butler matrix switched beam smart antenna system application has been designed and fabricated on 0.15-μm GaAs pHEMT process. By adopting inductive high impedance transmission lines in series-shunt switch topology, the SPQT switch demonstrates an insertion loss of 1.25-3.53 dB from DC to 20 GHz, and the isolation is higher than 22 dB with a compact chip size of 1.5 mm2. The measured output 1 dB compression point (OP 1 dB) is 16 dBm at 12 GHz. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:2023-2026, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26993 [ABSTRACT FROM AUTHOR]

A 53-67 GHz wide locking range injection-locked frequency divider (ILFD) has been designed and fabricated using 0.13-μm CMOS process.By using forward body bias technique, the proposed ILFD demonstrates good performance of the wide locking range while maintaining low DC power consumption. Via a 0 dBm incident signal power, an input locking rage greater than 14 GHz (>23%) is achieved with 4 mW from supply voltage of 0.8 V. If the supply voltage further reduces to 0.6 V, the input locking rage is 6 GHz (10%) while consuming only 1.2 mW. Compared to previous reported works in high-speed CMOS FD, the presented ILFD achieves superior figure of merit (FOM). Without extra voltage control mechanisms to increase the locking range, this FD covers whole 57-64 GHz band is suitable for integration into a 60 GHz WPAN phase-locked loop system. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett 53:1386-1389, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.25989 [ABSTRACT FROM AUTHOR]

In this letter, a low-voltage and low-power 3.5-GHz low noise amplifier (LNA) is designed and fabricated using TSMC 0.18-μm MS/RF complementary metal-oxide-semiconductor field effect transistor (CMOS) technology. The complementary current-reused topology is utilized to achieve low dc power consumption while maintaining reasonable gain performance. Consuming 1.38 mW dc power from 0.6 V supply, the LNA achieves a small signal gain of 16.09 dB and a noise figure of 4.702 dB at 3.5 GHz. Compared with previously reported LNA, the MMIC has excellent FOM performance. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:145-147, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26463 [ABSTRACT FROM AUTHOR]