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This study investigates the effects of negative bias temperature (NBT) stress and irradiation on the threshold voltage (VT) of p-channel VDMOS transistors, focusing on degradation, recovery after each type of stress, and operational behavior under varying conditions. Shifts in VT (ΔVT) were analyzed under different stress orders, showing distinct influence mechanisms, including defects creation and their removal and electrochemical reactions. Recovery data after each type of stress indicated ongoing electrochemical processes, influencing subsequent stress responses. Although the ΔVT is not particularly pronounced during the recovery after irradiation, changes in subthreshold characteristics indicate the changes in defect densities that affect the behavior of the components during further application. Additionally, the findings show that the ΔVT during the NBT stress after irradiation (up to certain doses and conditions) remains relatively stable, but this is the result of a balance of competing mechanisms. A subthreshold characteristic analysis provided a further insight into the degradation dynamics. A particular attention was paid to analyzing ΔVT with a focus on predicting the lifetime. In practical applications, especially under pulsed operation, prior stresses altered the device’s thermal and electrical performance. It was shown that self-heating effects were more pronounced in pre-stressed components, increasing the power dissipation and thermal instability. These insights additionally highlight the importance of understanding stress-induced degradation and recovery mechanisms for optimizing VDMOS transistor reliability in advanced electronic systems.

This study aimed to comprehensively understand the performance and degradation of both p- and n-channel vertical double diffused MOS (VDMOS) transistors under bias temperature stress. Conducted experimental investigations involved various stress conditions and annealing processes to analyze the impacts of BT stress on the formation of oxide trapped charge and interface traps, leading to threshold voltage shifts. Findings revealed meaningful threshold voltage shifts in both PMOS and NMOS devices due to stresses, and the subsequent annealing process was analyzed in detail. The study also examined the influence of stress history on self-heating behavior under real operating conditions. Additionally, the study elucidated the complex correlation between stress-induced degradation and device reliability. The insights contribute to optimizing the performance and permanence of VDMOS transistors in practical applications, advancing semiconductor technology. This study underscored the importance of considering stress-induced effects on device reliability and performance in the design and application of VDMOS transistors.