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In this study, the effects of three distinctive contents of metal oxide [Iron Nickel Oxide (Fe2NiO4), Iron Oxide (Fe2O3), Nickel Oxide (NiO), and Indium Tin Oxide (ITO)] and carbon nanostructure [diamond (C)]-reinforced solder paste on melting behavior, hardness, spreading rate, and wetting angle after reflow soldering were differentiated. Each nanoparticle was mechanically mixed with SAC 305 solder paste to produce homogeneous nanocomposite solder alloys. Based on the results, the addition of nanoparticles slightly increased the melting point; except for the SAC 305-ITO and SAC 305-Diamond composite solder pastes. The SAC 305-ITO composite solder showed negligible effects, but the SAC 305-Diamond composite solder reduced the melting point. The SAC 305-Diamond composite solder exhibited a very high increment in solder hardness compared with other nanocomposite solder pastes. Reinforcement of 0.5 wt% diamond nanoparticles increased solder viscosity higher than other metal oxide nanoparticles. The flow rate of SAC 305-Diamond molten solder on Cu substrate decreased upon the nanoparticle addition during reflow soldering. The reduction in the spreading caused the enlargement in the wetting angle of solder paste. However, very low percentage of carbon nanostructure addition into molten solder alloys reduced the melting point and increased solder hardness with tolerable spreading rate and wetting quality, which enhanced solder reliability after reflow.

The phenomenon of tin pest has been known for hundreds of years. Tin is one of the most common materials used in electronic products and systems. It is found in solders, as a surface finish for printed circuit boards, and as plating for connectors. Tin pest is the formation of tin in the phase of α‑tin, which particularly happens in pure tin that transforms from white β‑tin to gray α‑tin at temperatures below 13.2 °C. In this phase, tin is a structurally weak and readily crumbly powder that is not acceptable in electronic systems that must be reliable at low temperatures. Understanding how tin pest occurs is important for evaluating electronic reliability. Although most electrical devices are not exposed to low temperatures for a long period, for many industries, such as automotive (Snow-Cats), telecommunications base stations (cell phone towers), military (weapons systems), space (satellites), and outdoor recreation, the electronics must be reliable at all temperatures. This paper presents a comprehensive review of the tin pest phenomenon research and focuses on new experimental data regarding the formation of tin pest effects. The data presented and analyzed here enable manufacturers to make the right decisions when choosing a tin-based alloy for low-temperature applications. Suggestions on how this information affects the lead-free industry and recommendations for future work to clarify and evaluate the occurrence of tin pest for electronic circuits are presented. Common arguments about the risks of using tin, especially whether tin alloys are acceptable for low-temperature applications and whether lead-free solders should be exempt from regulations, are also discussed. The common assumptions are: (1) lead-free alloys can be safely used in low-temperature applications if solder paste joining technology is used, and (2) joints from solder paste benefit from both the presence of flux residues and tin oxide particles, which combined make the allotropic transformation extremely unlikely. Based on the data discussed in this review, an appendix summarizes the tin-pest-retarding effects on lead-free alloying metals.

With miniaturization of the interconnect solder bumps, high current density causes serious reliability issues (stress, electromigration etc.) in electronic packages. Through Au stud bumping on the chips and following reflow of solder to produce hybrid interconnects, the eletromigration resistance may be improved by the intermetallics formed inside them due to their barrier effects on the atoms migration. Here, microstructures and reliabilities of Au stud with serial amounts of Sn-0.7Cu solder paste were studied through controlling size of stencil printing aperture. After reflow, AuSn, AuSn2 and AuSn4 formed from the surface of Au stud bump to the solder. A layer of (Cu,Au)6Sn5 with thickness of 3 μm existed at the interface near the Cu substrate with a scallop shape similar to Cu6Sn5. The fraction of intermetallics to the mixed joints varied with the solder amount. Shear strength decreased slightly when comparing with the sole solder joint due to large amounts of brittle intermetallics. Thermal aging resulted in many Kirkendall voids generated at the interfaces of Au stud and the solder, which further decreased the shear strength. The effect of solder amount on microstructural evolution and fracture modes was discussed. The hybrid interconnects showed a good electromigration resistance.

Nanoparticle reinforced lead-free solder has previously been studied by several investigators, but few studies have evaluated its reliability. In this study, resistor chip (RC) micro joints were soldered using nano-Al 2 O 3 particle reinforced Sn–Ag–Cu solder paste. The microstructure and reliability of RC micro joints having different nano-Al 2 O 3 contents (0, 0.25, 0.5 and 1.0 wt%) were investigated in detail. More than 40 solder joints for each condition were made and examined in order to achieve reliable data. The results indicated that nano-Al 2 O 3 particles refined the β-Sn grain size and enlarged the eutectic area of the micro solder joints. Those nanoparticles also reduced the IMC thickness of the Ni-solder and Cu-solder interfaces. Those effects can be attributed to the poor-wetting behavior of nano-Al 2 O 3 particles. The nano-Al 2 O 3 reinforcement mainly enhanced the reliability of the micro solder joints, but did not affect the strength of as-soldered joints obviously. The improvement of reliability was proportional to the nano-Al 2 O 3 content. The microstructure and fracture analysis indicated that the reinforcement and stability of Ni-IMC and Cu-IMC interfaces accounted for better reliability.

This article is focused on both macro and microvoids in soldered joints and the use of additional flux to reduce their frequency and minimize their negative effect on the soldered joint reliability. In total five fluxes were used, three were gel based (NC559, MTV-125R, TSF-6516) and two of them were liquid based (Topnik G-5, JBC FL-15). They were used within two solder pastes, both lead and lead-free. The reflow process was identical for all of the combinations and was within the range of manufacturer recommended profiles. The amount of voids was evaluated using X-ray analysis. It was found that the use of increased amount of proper flux, specifically flux with higher activity, in the solder paste may significantly lower the void occurrence.

With the current high demand for energy saving and low power consumption, numerous studies have been conducted to meet this requirement. Higher switch efficiency is one of the factors for power saving in power inverters and converters. Among the methods for improved switch efficiency, the modified package structure is one of the solutions. An embedded power module enables shortened transmitting routes and lower parasitic reactions, suggesting better power switching performance. Meanwhile, embedding allows the power devices to integrate active or passive devices above or beneath a component, leading to a three-dimensional packaging structure. This feature is also applicable in the integration of power devices because of its double side contact structure. Four dies that contain two insulated gate bipolar transistors and two diodes in this study were embedded and integrated in a carrier substrate to produce a next-generation power inverter module. The process began by attaching a die on a Cu lead frame by a SAC305 solder paste. This is followed by a lamination process to form a built-up dielectric layer on the Cu lead frame. The conducting vias and circuits were formed on the built-up dielectric layer by a UV laser and were metalized with sputtered seed layer and electroplating. The circuit layout can be revealed with subsequent etching processes by hatching another layer of electroplated Sn using UV laser. Finally, a layer of solder mask was printed to prevent electric shock on the surface layer. Structure and process features are discussed, and electrical testing and reliability tests are conducted in this paper.

Thermo-electric modules can be used to convert heat into electricity by utilizing the Seeback effect. It is now possible to buy BiTe thermo-electric modules that can operate up to temperatures of around 300°C. However, many applications, such as the harvesting of exhaust gas from large vehicles or gas turbine heat, may occur at higher temperatures Therefore, new materials and manufacturing processes need to be developed to produce packaged TEM that can operate at a maximum operating temperature of 650°C. Two critical areas in the manufacture of a SiGe TEM are the choice and strength of materials used to both solder the TE material to the rest of the module and the metal used for the interconnects. The interconnection material needs to be sufficiently strong to withstand large temperature fluctuations while maintaining a low contact resistance, as well as being compatible with the nano-Ag solder. Shear force tests of the sintered thermo electrical leg material showed that the joints are brittle when sintered to W metallized AlN substrates are used and ductile fracture behavior when sintered to Cu metallized AlN substrates using the NanoTach K nano silver paste. Almost all of the joints were found to be brittle when using the NachTach X nano silver paste. Shear testing of the solder joints showed that the X paste joints were variable in strength and stiffness, having a typical Young's modulus between 10 and 100 MPa at room temperature. The K paste joints were stiffer, but had a similar strength as compared to the X paste joints.

Conductive adhesives play a major role in the electronic packaging industry as an alternative to solder due to their potential advantages that include mild processing conditions and superior thermo-mechanical performance. In a conductive adhesive interconnection, adequate mechanical and electrical performance and long-term reliability are critical. In this paper, the reliability of solderable isotropic conductive adhesive (ICA) interconnections was investigated. Reliability testing was performed via thermal shock (−55 to 125 °C, 1000 cycles) and high-temperature and high-humidity tests (85 °C, 85% RH, 1000 h). The interfacial microstructure of the solderable ICA was also investigated. Additionally, the fracture mode was investigated via mechanical pull strength testing before and after the reliability test. The electrical resistance of the solderable ICA interconnection showed improved stability compared to conventional ICAs, and similar stability to conventional solder paste (Sn–3Ag–0.5Cu and Sn–58Bi) due to the metallurgical interconnection formed by the molten LMPA fillers between the corresponding metallization layers. After the reliability tests, the grown IMC layer was composed of Cu6Sn5 (η-phase) and Cu3Sn (e-phase), and the scallop-type IMC transformed into a layer-type IMC. The fracture propagated along the Cu–Sn IMC/SnBi interface and the fracture surface showed a semi-brittle fracture mode mixed with cleavage and ductile tear bands.

This paper investigates the effect of void percentage in the solder layer on the shear strength and thermal property of DA3547 packages by SAC soldering technology. X-ray observation and shear tests revealed that the increase of solder paste volume significantly decreases the void percentage in the solder layer and thus improved the shear strength of the packages. Furthermore, packages with lower void percentage showed a lower junction temperature based on the results of IR test and finite element simulation. The temperature difference due to the effect void percentage shows a correlation with the input power. For the DA3547 packages studied in this research, voids show limited influence on the junction temperature under 50 mA, the typical current recommended by Cree.

Experimental studies of void formation were performed using a solder paste with a small particle size and a thin substrate with a small solder resist opening (SRO) size. Two kinds of Sn–Ag–Cu solder paste, screen printing mask opening (MO) size and pad finishes, and three kinds of SRO sizes were used as process variables. In this study, paste type and MO size had little influence on the formation of voids. In general, fewer voids were formed using the electroless nickel electroless palladium immersion gold (ENEPIG) pad finish than the organic solderability preservative (OSP) pad finish. However, the suitability of the pad finish was different depending on the type of paste. Void formation reduced with decreasing SRO. Both focused ion beam cross-sectioning and a thermal video system were used to ascertain the mechanism of void formation when using the paste with a small particle size, and the entrapment of flux was identified as the main cause for the formation of voids.

As from July 1, 2006, the European Union officially enforced prohibition of the use of six designated hazardous substances under the restriction of hazardous substances (RoHSs), including lead, cadmium and others. In addition, as from 2008, the requirements of green products had been made stricter by adding prevented use of halogen as the standard. When confronted with the two harsh lead-free and halogen-free conditions, the customary input settings of soldering manufacturing process by using surface mount technology (SMT) faces tremendously challenged. Therefore, to improve the reliability of electronic products in the entire lead-free and halogen-free SMT-green process, this study performs comprehensive experiments and employs analysis and improvement methods including the experimental design, analysis of variance, and statistical process control to determine the optimal combination of soldering conditions for the integrated-circuit solder ball of ball grid array (BGA). The results conclude aspects of the utilization method of solder paste, setting of parameters for solder printer, the temperature profile for the reflow oven, the proportion of pad to solder paste amount, and brand selection of the solder paste. Overall, the average soldering strength improves from 165.5 to 298.3gf, which is 80.24% increase. In general, this study allows electronic industry to consider environmental concerns along with the traditionally evaluated parameters of reliability and cost.

The poor drop-shock resistance of near-eutectic Sn–Ag–Cu (SAC) solder interconnects drives the research and application low-Ag SAC solder alloys, especially for Sn–1.0Ag–0.5Cu (SAC105). In this work, by dynamic four-point bend testing, we investigate the drop impact reliability of SAC105 alloy ball grid array (BGA) interconnects with two different surface mounting methods: near-eutectic solder paste printing and flux dipping. The results indicate that the flux dipping method improves the interconnects failure strain by 44.7% over paste printing. Further mechanism studies show the fine interfacial intermetallic compounds (IMCs) at the printed circuit board side and a reduced Ag content inside solder bulk are the main beneficial factors overcoming other negative factors. The flux dipping SAC105 BGA solder joints possess fine Cu6Sn5 IMCs at the interface of solder/Cu pads, which increases the bonding strength between the solder/IMCs and the fracture resistance of the IMC grains themselves. Short soldering time of flux dipping joints above the solder alloy liquidus mitigates the growth of interfacial IMCs in size. In addition, a reduced Ag content in flux dipping joint bulk causes a low hardness and high compliance, thus increasing fracture resistance under higher-strain rate conditions.

We tested the ability of Au/Sn eutectic, silver paste, and solder paste to bond to a large area as well as the bonding of a high power LED die to a highly conductive submount. The samples ran through several tests including ultrasound image, shear force, and thermal resistance measurement. Finite element analysis (FEA) models were built for comparison and analysis. Au/Sn bonding shows the best thermal and mechanical properties. Silver paste shows lower contact thermal resistance compared with solder paste. Although the thickness of the silver paste bonding layer is greater than the solder paste bonding layer, the average total thermal resistance is noticeably lower than the solder paste bonded samples.

In the mass assembly of today’s electronic circuits, solder paste is first printed onto the surface of the assembly boards through a metal mask called a stencil. The possible surface differences in level on the PWB, e.g. marking stickers or other protruding objects keep the stencil away from the PWB during stencil printing, can cause excessive printed volume of the solder paste, and solder bridges or other soldering failures can occur after reflow soldering. If these differences in level are not too high or they are sufficiently far from the soldering pads in lateral direction, the stencil can bend down to the pad during stencil printing and the volume of the deposited solder paste will be as expected. In our research a Finite Element Model (FEM) was created to investigate the stencil deformation and to determine the necessary distance between the pads and the local differences in level to achieve complete stencil contact to the PWB. A simple deformation measuring set-up was designed and fitted together to experimentally determine the mechanical parameters of the stencil and the squeegee, which were necessary for the FEM. PWB surface differences in level in the range of 0–90 μm and stencil foil thicknesses varying between 75 and 175 μm were inserted into the FEM as geometrical parameters and simulations were executed to calculate the minimum distances which are necessary to achieve perfect stencil contact to the PWB. The FEM was verified by comparing simulation results to experimental results obtained by real stencil printing.

a b s t r a c t Sn-9Zn solder joints containing Ag nano particles were prepared by mechanically mixing Ag nano parti- cles (0.3, 0.5 and 1 wt%) with Sn-9Zn solder paste. In the monolithic Sn-Zn solder joints, scallop-shaped AuZn 3 intermetallic compound layers were found at their interfaces. However, after the addition of Ag nano particles, an additional uniform AgZn 3 intermetallic compound layer well adhered to the top surface of the AuZn 3 intermetallic compound layer was found. In addition, in the solder ball region, fine spher- ical-shaped AgZn 3 intermetallic compound particles were observed as well as Zn-rich and b-Sn phases. With the addition of Ag nano particles, the shear strengths consistently increased with an increase in the Ag nano particle content due to the uniform distribution of fine AgZn 3 intermetallic compound par- ticles. The shear strength of monolithic Sn-Zn and 1 wt% Ag nano particle content Sn-Zn solder joints after one reflow cycle were about 42.1 MPa and 48.9 MPa, respectively, while their shear strengths after eight reflow cycles were about 39.0 MPa and 48.4 MPa, respectively. The AgZn 3 IMCs were found to be uniformly distributed in the b-Sn phase for Ag particle doped Sn-9Zn composite solder joints, which result in an increase in the tensile strength, due to a second phase dispersion strengthening mechanism. The fracture surface of monolithic Sn-Zn solder exhibited a brittle fracture mode with a smooth surface while Sn-Zn solder joints containing Ag nano particles showed a typical ductile failure with very rough dimpled surfaces.

Reliability of QFP (quad flat package) solder joints after thermal shock was investigated for PCB’s and connecting leads plated with several different alloy coatings before soldering. Sn–8 wt%Zn–3 wt%Bi (hereafter, Sn–8Zn–3Bi) was selected as a solder, and FR-4 PCB’s finished with Cu/Sn, Cu/OSP and Cu/Ni/Au were used as substrates. The leads of the QFP were Cu plated with Sn–10 wt%Pb, or Sn, or Sn–3 wt%Bi. The QFP chips were mounted on the substrates using a Sn–8Zn–3Bi solder paste and reflowed in air atmosphere. The pull strength and microstructure for the soldered leads of QFP were evaluated before and after thermal shock testing. The leads plated with Sn or Sn–3Bi showed approximately 40–50% higher pull strength than the reference value of a Sn–37%Pb solder joint for all PCB-finishes. However, in the case of leads coated with Sn–10Pb, the pull strength of the leads soldered to a Sn-finished PCB was 21% lower than the reference value. In microstructure analysis of the joints with Sn–10Pb-plated leads, cracks were found along the bonded interface for Sn-finished PCB. The cracks were believed to start from the low melting temperature phase, 49.38 wt% Pb–32.58 wt%Sn–18.03 wt%Bi, found around the crack, and then propagated through Cu–Zn intermetallic compound. Meanwhile, even when using Sn–10Pb-plated leads, the PCB’s finished with Cu/Ni/Au coating had about 30% higher strength than the reference value, and cracks were hardly found on the soldered joint. Thus, even with Sn–10Pb-plated leads the Cu/Ni/Au-finished PCB’s were evaluated to be as reliable as the reference joint.

The results of the influence of lead-free solder paste, design and process parameters on the attachment reliability of chip surface-mounted components (SMCs) on thick-film conductor pads are presented. The purpose of the investigation was to compare the quality of the soldered joints made with new solder pastes that do not contain lead with joints soldered with standard SnPb solders. The miniature zero-ohm chip resistors were soldered with selected lead-free solder pastes. The visual appearance of the solder joint according to the standards of lead-free soldered components was compared with components soldered with SnPb solders. On the test sample with soldered chip resistors connected in series, the solder-joint resistance was measured before and after temperature cycling. On the same test sample the solder-joint resistance changes were measured with impedance spectroscopy. After temperature cycling the damaged samples were analysed with SEM and EDS. The reliability test results after temperature cycling indicate two lead-free solder pastes that are the most convenient for chip-component soldering on thick-film conductor pads with the reliability of the joints being equal or better than solder joints with Pb-containing solder paste.

In this study, microstructure evolution at intermetallic interfaces in SnAgCu solder joints of an area array component was investigated at various stages of a thermal cycling test. Failure modes of solder joints were analyzed to determine the effects of process conditions on crack propagation. Lead-free printed-circuit-board (PCB) assemblies were carried out using different foot print designs on PCBs, solder paste deposition volume and reflow profiles. Lead-free SnAgCu plastic-ball-grid-array (PBGA) components were assembled onto PCBs using SnAgCu solder paste. The assembled boards were subjected to the thermal cycling test (−40 °C/+125 °C), and crack initiation and crack propagation during the test were studied. Microstructure analysis and measurements of interface intermetallic growth were conducted using samples after 0, 1000, 2000 and 3000 thermal cycles. Failures were not found before 5700 thermal cycles and the characteristic lives of all solder joints produced using different process and design parameters were more than 7200 thermal cycles, indicating robust solder joints produced with a wide process window. In addition, the intermetallic interfaces were found to have Sn–Ni–Cu. The solder joints consisted of two Ag–Sn compounds exhibiting unique structures of Sn-rich and Ag-rich compounds. A crystalline star-shaped structure of Sn–Ni–Cu–P was also observed in a solder joint. The intermetallic thicknesses were less than 3 μm. The intermetallics growth was about 10% after 3000 thermal cycles. However, these compounds did not affect the reliability of the solder joints. Furthermore, findings in this study were compared with those in previous studies, and the comparison proved the validity of this study.

The trend towards smaller, faster and cheaper electronic devices has led to an increase in the use of 0201 (L ∼ 0.02 in.; W ∼ 0.01 in.) and even smaller sized passive components. The size advantages of the 0201 component make it a popular choice among design engineers but not among manufacturing engineers. From a manufacturing perspective, the size of the 0201 package poses significant challenges to the printed circuit board (PCB) assembly process. The many challenges with 0201 assembly can be attributed to the solder paste volume, pad design, aperture design, board finish, type of solder paste, pick-and-place and reflow profile. If these factors are not optimized, they will introduce undesirable manufacturing defects. The small size of 0201 packages and undetected manufacturing defects will also raise concerns about their second level interconnect reliability, especially for lead-free solder alloys and surface finishes, with new processes and higher reflow requirements. To determine the optimum conditions, a design-of-experiment (DOE) study was carried out to investigate the effects of these parameters on assembly defects and solder joint reliability. This paper presents the test results and comparative literature data on the influence of a few key manufacturing parameters and defects associated with the 0201 component using lead-free and tin–lead solder alloys. Data pertaining to component shear strength before and after isothermal aging at 150 °C and intermetallic growth up to 500 h of aging are presented. A number of test vehicles were also subjected to thermal cycling (1500 cycles) in the range of −55/100 °C to determine the solder fatigue behavior. Shear test results for test vehicles subjected to thermal cycling is also presented. In addition, optical microscopy analysis of solder joint behavior during thermal cycling showing the progress of the solder damage and cross-sectional photos taken at 1500 cycles is included.

An experimental investigation was combined with a non-linear finite element analysis using an elastic–viscoplastic constitutive model to study the effect of ball shear speed on the shear forces of flip chip solder bumps. A solder composition used in this study was Sn–3mass%Ag–0.5mass%Cu. A low cost bumping process has been employed using electroless Ni and immersion Au followed by solder paste stencil printing. A thin layer of intermetallic compound, (Ni 1− x Cu x ) 3 Sn 4 , was formed by the reaction between the solder and electroless Ni with a thickness of about 1.4 μm, while some discontinuous (Cu 1− y Ni y ) 6 Sn 5 particles were also formed at the interface. The compositions of the resulting compounds were identified using energy dispersive spectrometer (EDS) and electron microprobe analysis (EPMA). Shear tests were carried out over a shear speed range from 20 to 400 μm/s at a shear ram height of 20 μm. The shear force was observed to linearly increase with shear speed and reach the maximum value at the fastest shear speed in both experimental and computational results. The optimum shear speeds for the shear test of solder bumped flip chip were recommended to be not exceeding 200 μm/s. The failure mechanisms were discussed in terms of von Mises stresses and plastic strain energy density distributions.

In the past few years, many studies have reported on the formula of solder metal alloy materials. This paper discusses the influence of organic materials characters, the decomposing rate of flux in lead-free solder paste and coefficients of thermal expansion (CTE) of halogen-free mold compounds during the on-board reliability test, and the failure mechanism in both 63Sn/37Pb and Sn–3.5Ag–0.5Cu lead-free solder balls was reported. The thermal decomposing behavior of flux in the solder paste induced voids in solder joints was examined by thermo-gravimetric analysis (TGA) and X-ray perspective, respectively. On-board temperature cycle test (TCT) reliability failed specimens were sectioned and analyzed by the optical microscope (OM) and X-ray. The evolutions of package warpage change of two kinds of potential halogen-free compounds during the TCT reliability process were monitored by specially designed thermal mechanic analysis (TMA) experiments. The experimental results show that higher IR-reflow peak temperature induced voids forming in the solder joints and then failure mode change from interface between intermetallic and solder to cracks cut across the big voids during TCT test, worse TCT reliability performance ensued. Moreover, according to on-board reliability testing data show that the compound with larger package warpage change generated larger cumulate plastic work in solder joint that caused early failure during TCT process.

We have implemented a company-wide effort to progressively reduce the use of Pb(lead) and eventually eliminate this environmental pollutant from its products. As part of this effort, it has developed a new lead-free solder that consisting of Sn(tin), Zn(zinc), and Al(aluminum) and yet offers superior productivity and joint reliability. The new lead-free solder has a melting point equivalent to that of a SnPb eutectic solder, and enables devices to be packaged at a lower temperature than with the increasingly popular Sn(tin), Ag(silver), Cu(copper) solder. Thus, the new lead-free solder accelerates the elimination of Pb from products. we have already used printed circuit boards containing the new lead-free solder in some products, and plans to extend its use to other products. We further mounted SnZnAl solder balls onto Cu/Ni(nickel)/Au(gold) plated polyimide substrate at a joining temperature of 215 °C for CSP applications. It was confirmed that the joint interface between soldered ball and substrate at the initial stage was made of 2-layered compounds, i.e., AuZnSn on soldered side and ZnSnNi on substrate side. After 1000 h aging at 150 °C, the two layers compounds become one layer of ZnSnNiAu compound. No strength deterioration of Cu/Ni/Au/SnZnAl after the 1300 h shelf test was detected in the ball shear strength compared with the initial value. This paper describes the characteristics of the new lead-free solder and the results of a study on its solder ball CSP package.

The paper presents creep data, that was gained on specimens of different microstructures. The three specimen types have been flip chip solder joints, pin trough hole solder joints and standard bulk solder specimens. The bulk solder specimen was a dog-bone type specimen (diameter=3 mm, length=117 mm). The pin trough hole solder joint consisted on a copper wire that was soldered into a hole of a double sided printed circuit board (thickness 1.5 mm). The flip chip solder joint specimen consisted of two silicon chips (4 mm × 4 mm), which were connected by four flip chip joints (one on each corner). SnAg and SnAgCu flip chip bumps (footprint 200 μm × 200 μm, joint height 165–200 μm, centre diameter 90…130 μm) were created by printing solder paste. Constant–load creep tests were carried out on all three specimen types at temperatures between 5 and 70 °C. Creep data was taken for strain rates between 10 −10 and 10 −3 s −1 . The specimens were tested in “as cast” condition and after thermal storage. The microstructural properties of the bulk specimens and real solder joints were examined using metallographic sectioning, optical microscopy techniques, and SEM-microprobe analysis. The results of the microstructural analysis were related to the investigated mechanical properties of the solders. Models of SnAg3.5 and SnAg4Cu0.5, that can be used with the ANSYS FEM software package, will be presented.

Stencil printing remains the technology route of choice for flip chip bumping because of its economical advantages over traditionally costly evaporation and electroplating processes. This paper provides the first research results on stencil printing of 80 and 60 μm pitch peripheral array configurations with Type 7 Sn63/Pb37 solder paste. In specific, the paste particle size ranges from 2 to 11μm with an average particle size of 6.5 μm taken into account for aperture packing considerations. Furthermore, the present study unveils the determining role of stencil design and paste characteristics on the final bumping results. The limitations of stencil design are discussed and guidelines for printing improvement are given. Printing of Type 7 solder paste has yielded promising results. Solder bump deposits of 25 and 42 μm have been demonstrated on 80 μm pitch rectangular and round pads, respectively. Stencil printing challenges at 60 μm pitch peripheral arrays are also discussed.

A brittle solder joint at the interface between a solder ball and a substrate metal pad could result in an open joint failure after the solder ball is attached to a motherboard. Existing metrologies, such as ball shear, do not always detect the weak solder joint strength. A peel test for solder joint strength evaluation of substrate was developed. Several problems were observed during the initial stages of the development for this metrology. These included solder bridging and inconsistency of the test results. Solder bridging was reduced by changing the stencil design to have stencil openings that match the solder ball layout and using a jig to align the coupon and substrate while assembling the peel test samples. The paste printing and peeling methods were modified and the coupon quality was carefully monitored to make the sample preparation and testing more consistent. The impact of the physical aging and reflow on the solder joint strength was investigated. It showed that the peel strength did not decrease with physical aging, but did decrease with an increased number of reflows. The peel test results correlated with the performance of the substrates. The substrate with low peel strength had weak solder joints and failed under use conditions. The substrates with high peel strength demonstrated stronger solder joints and performed well under use conditions. The metrology provides a gross check about the presence of brittle solder joints on flip chip ball grid array substrates and is successfully used in monitoring the solder joint strength.

As the electronics industry is moving towards lead-free manufacturing processes, more effort has been put into the reliability study of lead-free solder materials. Various tin–silver–copper-based solders have become widely accepted alternatives for tin–lead solders. In this study, we have tested three different SnAgCu solder compositions. The first consisted of a hypoeutectic 96.5Sn/3.0Ag/0.5Cu solder, the second of a eutectic 95.5Sn/3.8Ag/0.7Cu solder, and the third of a hypereutectic 95.5Sn/4.0Ag/0.5Cu solder. A eutectic SnPb solder was used as a reference. The test boards were temperature-cycled (−40 to +125 °C) until all samples failed. The results of the temperature cycling test were analyzed, and cross-section samples were made of the failed joints. Scanning electron and optical microscopy were employed to analyze the fracture behavior and microstructures of the solder joints. The reliability of lead-free solders and the effect of microstructures on joint reliability are discussed.