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This paper characterizes fracture strength of a silicon die as a first step to predict and prevent die cracking during package assembly, reliability tests, and operation life. Die strength is measured via the three-point bend test conducted using a micro-force tester. Strength reduction due to surface defects, such as tiny notches or micro-cracks that are introduced through wafer backside grinding is evaluated. It is observed that die strength strongly depends on the grinding patterns, i.e. minimum die strength in a wafer is found if the grinding mark is in parallel with the loading axis. Furthermore, fracture strength of dies with different wafer surface conditions like polishing and no treatment (grinding) are also examined. Polished wafers possess the highest silicon strength owing to its minimum surface flaws. On the other hand, untreated wafers contain the most severe surface defects; hence exhibit the lowest die strength. Geometrical factors (square vs. rectangular) and die thickness (4 vs. 6 mils) are probed as well, however these factors do not contribute to die strength degradation. Surface morphology and roughness studies of silicon dies via scanning electron microscope and atomic force microscope also confirmed that die strength degradation is mainly controlled by surface defect (roughness) levels. Observed fracture modes also correlate well with measured die strength. [Copyright &y& Elsevier]

This paper aims to measure and simulate the warpages of 3D through-silicon via (TSV) die-stacked dynamic-random-access-memory (DRAM) packages during the manufacturing process. The related die stresses and keep-out zone (KOZ) for the stacked dies in the packages at room temperature are further calculated with the validated simulation model. The out-of-plane deformations (or warpages) of the packages from the full-field shadow moiré are documented under temperature loading and found consistent with those from finite-element method (FEM). The results of the stresses and KOZs at the proximity of a single TSV for each die in the package at room temperature are presented. It is found that the sizes of KOZs in four-die stacked DRAM packages with and without epoxy molding compound (EMC) at room temperature are dominated by the horizontal pMOS transistors and more than double the size in wafer-level die. The sizes of KOZs at each die are similar in this four-die stacked DRAM package, even though the stresses at each die are apparently different. [ABSTRACT FROM AUTHOR]

Abstract: Even though recently published results indicated that residual strains of the epoxy molding compound (EMC) play a key role on the warpage values and shapes of the plastic ball grid array (PBGA) packages, it is still unknown about how these residual strains build up and change during the manufacturing and infrared (IR) solder reflow processes. The purpose of this study is to quantify the residual strains of the EMC in the PBGA packages during the aforementioned processes using a combination of experimental, theoretical and numerical approaches. In the experiments, a full-field shadow moiré is used for measuring their real-time out-of-plane deformation (warpage), during heating and cooling conditions, of two types of the PBGA specimens (without a silicon chip inside) with the same EMC but different substrates (with glass transition temperature T g =172 and 202°C). Furthermore, Timoshenko’s bi-material theory associated with the measured and temperature-dependent elastic moduli and coefficients of thermal expansion for the EMC and substrates is applied for extracting residual strains of the EMC from shadow moiré results. In the analysis, the finite element method cooperating with those determined residual strains is employed to numerically simulate the thermal-induced deformations of the PBGA specimens, in order to verify mechanics. The full-field warpage of the specimens from shadow moiré is documented before and after post-mold curing, solder reflow and during the temperature cycling (from room temperature to 260°C). The residual strains of the EMC for the specimens with low-T g and high-T g substrates after post-mold curing are found to be 0.059% and 0.134%, respectively, which double those before post-mold curing, and further down to 0.035% and 0.08% after the first thermal cycling. After the first cycling, the residual strains remain almost constant during heating and cooling processes. This phenomenon is also observed at lead-free solder reflow processes. Therefore, the residual strains of the EMC induced by the chemical shrinkage of the EMC curing and possibly mold flow pressure are different between the specimens with low-T g and high-T g substrates, and these residual strains could change during post-mold curing and the first solder reflow processes. [Copyright &y& Elsevier]

Second (board) level reliability of a stacked chip scale package (SCSP) under cyclic bending is conducted to evaluate the structural integrity of solder interconnects. The test vehicle (on-board SCSP) is simply supported at both ends and subjected to repetitive deflection in the middle (three-point bend). Cyclic deformation histories such as sinusoidal, triangular, and square waveforms are examined. Tremendous joint damage is observed as square-wave loading history was applied. Approximately 80% fatigue life degradation is found by bending several thermally aged samples having Ni/Au surface finish on Cu pads of package substrates and printed circuit boards. The observed failure mode is a brittle type fracture of intermetallic compound system, which is also known as effects of solder embrittlement.Measured fatigue life is characterized by two-parameter Weibull model with cumulative damage plot for each test condition. In addition to the comparisons of characteristic fatigue life for various package configuration and cyclic bending conditions, failure analysis is also employed to identify failure sites and mechanisms such as crack initiation and continuous growth to the complete fracture of solder joints. [Copyright &y& Elsevier]

Abstract: Process precision index C p has been widely used in the manufacturing industry to provide numerical measures of process precision, which essentially reflects product quality consistency. Precision measures using C p for normal processes, contaminated normal processes, have been investigated extensively, but are neglected for truncated normal processes. Truncated normal processes are common in the manufacturing industry, particularly, for factories equipped with automatic machines handling fully inspections, and scrap/rework products falling outside the specification limits. If the processes follow the normal distribution, then the inspected products (processes) must follow the truncated normal distribution. In this note, we consider the precision measure for truncated normal processes. We investigate the analytically intractable sampling distribution of the estimated C p, and obtain a rather accurate approximation. Using the results, we develop a practical testing procedure for practitioners to use in their in-plant applications. [Copyright &y& Elsevier]