Back to Search
Start Over
An investigation into warpages, stresses and keep-out zone in 3D through-silicon-via DRAM packages.
- Source :
-
Microelectronics Reliability . Dec2014, Vol. 54 Issue 12, p2898-2904. 7p. - Publication Year :
- 2014
-
Abstract
- This paper aims to measure and simulate the warpages of 3D through-silicon via (TSV) die-stacked dynamic-random-access-memory (DRAM) packages during the manufacturing process. The related die stresses and keep-out zone (KOZ) for the stacked dies in the packages at room temperature are further calculated with the validated simulation model. The out-of-plane deformations (or warpages) of the packages from the full-field shadow moiré are documented under temperature loading and found consistent with those from finite-element method (FEM). The results of the stresses and KOZs at the proximity of a single TSV for each die in the package at room temperature are presented. It is found that the sizes of KOZs in four-die stacked DRAM packages with and without epoxy molding compound (EMC) at room temperature are dominated by the horizontal pMOS transistors and more than double the size in wafer-level die. The sizes of KOZs at each die are similar in this four-die stacked DRAM package, even though the stresses at each die are apparently different. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 00262714
- Volume :
- 54
- Issue :
- 12
- Database :
- Academic Search Index
- Journal :
- Microelectronics Reliability
- Publication Type :
- Academic Journal
- Accession number :
- 99794462
- Full Text :
- https://doi.org/10.1016/j.microrel.2014.08.017