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Abstract: Realising a higher voltage application utilising bridge topologies in CMOS Power IC CMOS technology presents integration and design issues that must be solved by careful selection of the manufacturing process architecture. In this paper, we present a solution that uses a p+/p-buffer/n-epi stack to implement a 100V RESURF N-channel LDMOS high-side compatible power transistor. The device was developed and designed onto the new substrate using TCAD industrial standard softwares (TSuprem4 and Medici). Masks were designed using the Cadence Virtuoso tool set. The physical results show good transistor characteristics compatible for high-side applications. The specific resistance, RDSon, for the new device is 175mΩmm2 and breakdown voltage for both high-side and low-side operations exceeds targeted 100V. The design involved new starting material, and the test structures to measure latch-up susceptibility were also designed and manufactured. These structures were characterised and the results show minimal degradation in standard CMOS performance. [Copyright &y& Elsevier]

Abstract: A combination of two conventional junction isolation structures is used to produce a device, which significantly improves the blocking of minority carriers injected into the substrate of a power IC due to switching of an inductive load. Simulation results show that the connection scheme employed greatly enhances the efficiency of the structures. A substrate current reduction of up to four orders of magnitude compared to conventional junction isolation structures is achieved. The significance of doping profiles in the p-sinker region is evaluated. [Copyright &y& Elsevier]