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Gallium nitride (GaN)-based digital integrated circuits (ICs) are constructed on the commercially available GaN-on-Si wafer designed for pGaN gate HEMT. The functions of inverter, NAND, AND, NOR, and OR logic circuits are successfully realized based on direct-coupled field-effect transistor logic (DCFL) structure. Under a drive voltage of 5V and a load ratio of 20, the low output (VOL) can reach as low as 0.1V. Additionally, a functional-oriented driver, a SR flipflop, and a NOR gate D flipflop are constructed. All the transient tests at a frequency of 100 kHz and temperatures up to 200 °C exhibit satisfying performance characteristics. [ABSTRACT FROM AUTHOR]

As IC transistors scale down further, physical limitations are restricting performance growth. The contradiction between demands for computing capabilities and challenges in transistor downscaling is exacerbating. This paper proposed a crosstalk circuit design using interconnect coupling capacitance to improve the computing power of chips. Firstly, a valid model of coupling capacitance between metal interconnects is established based on analysis of the factors affecting coupling capacitance. Then, basic crosstalk gates including NAND and NOR are designed by adopting line crosstalk and sampling inverters. Furthermore, complex logic gates and combination circuits are implemented by using the basic crosstalk gates. For verification, a test chip based on line computing is fabricated in 65 nm CMOS technology and the core area is ∼0.019 mm2. The experimental results verified the correctness of the proposed crosstalk gate's logic. Compared with standard logic circuit, the crosstalk NAND or NOR gates reduce the area overhead by 10.6 % and also enhance the circuit's capability of anti-reverse engineering. [ABSTRACT FROM AUTHOR]

Resistive random access memory (RRAM) is viewed as the next-generation memory model, surpassing the constraints of traditional random access memory. Given its non-volatile nature, which lessens static power consumption, RRAM boasts significant computing-in-memory (CIM) potential. We herein present a four-transistor/two-resistor cross-coupling structure based on RRAM. In this structure, two RRAMs are situated in opposite directions, a configuration referred to as reverse coding. This structure provides the flexibility and reconfigurability to adjust the RRAM connections, facilitating various CIM operations in fewer cycles. A full adder design was developed and its feasibility was validated through simulations. Monte Carlo analysis ensures the accuracy of logic operations, even while encountering significant resistance fluctuations. This approach effectively mitigates the resistance crossover observed in existing RRAM CIMs. Compared with previous methodologies, the proposed structure achieves greater robustness with fewer cycle counts and RRAM numbers, The comparison of our approach with state-of-the-art Boolean logic circuits for RRAM architecture shows significant improvement in both delay (1.4–4.1 ×) and the number of RRAM (1.2–6.6 ×). [ABSTRACT FROM AUTHOR]

The performance of a silicon nanotube-based feedback field-effect transistor (SiNT FBFET) with a core-source architecture has been explored in this work for the use in logic-in-memory (LIM) applications. Both n-channel and p-channel FETs with extremely symmetric transfer characteristics and a high O N / O F F current ratio of 10 9 are implemented in a single structure using the core and outer gates. SiNT FBFET exhibits significant data retention attributes during memory operations for up to 10 3 s. The SiNT FBFET-based inverter circuit retains output logic states of "1" and "0" for 1.705 s and 1.948 s, respectively, at megahertz operating frequency without standby power consumption. Additionally, SiNT FBFET has also been used to build ternary NAND/NOR logic gates with memory functionality. Numerical mixed-mode simulations of the circuits have been carried out using the commercially available Synopsys "Sentaurus" TCAD tool for examining the performance and memory characteristics of SiNT FBFETs. This study demonstrates the possible use of SiNT FBFET in multivalued logic systems and the development of next-generation memory devices. • A reconfigurable silicon nanotube-based FBFET with a high O N / O F F current ratio of 10 9 and symmetrical current–voltage characteristics for both n and p-channel modes of operation is demonstrated. • A high retention time of 10 3 s in O N / O F F states for both n- and p-channel modes of operation has been observed. • The device achieves superior retention times for output logic states (1.705 s for '1' and 1.948 s for '0') without standby power consumption, aiding in designing logic-in-memory (LIM) features for an inverter. • Universal ternary NAND (TNAND) and ternary NOR (TNOR) logic gates with memory operations have been successfully implemented using SiNT FBFETs. [ABSTRACT FROM AUTHOR]

The proposal of compute-in-memory (CIM) is a breakthrough for the traditional von Neumann architecture to achieve efficient computing research. This architecture has unique advantages in the computing field thanks to supporting multi-line computing and without data transmission between processor and memory. In this paper, an in-memory computing structure based on 9T SRAM unit is proposed, which can both operate on memory and computing mode. Compared with the previous works, thanks to the redundant units, the computational structure can directly complete XNOR operations and storage of the whole SRAM array in only one cycle, without the need of extra digital logic circuits (such as AND, OR circuits), which can significantly improve the parallelism of the computation. Meanwhile, the architecture can map the XNOR logical operation into the binary multiplication, and then add up the one-bit multiplication results through the addition tree, thus realizing the binary convolution calculation. A 64-bit × 64-bit (4 Kb) SRAM array with the proposed scheme is designed and simulated in 55 nm CMOS technology. Simulation results show excellent stability and write yields in SRAM memory mode at an operating frequency of 200 MHz. In computing mode, the SRAM array power consumption for logical operation is 52.68 fJ/bit at 1.2 V supply voltage. At a minimum supply voltage of 0.8 V, the power consumption is only 5.58 fJ/bit, with an energy efficiency 179.21 TOPS/W. [ABSTRACT FROM AUTHOR]

The Gate Level Information Flow Tracking (GLIFT) is an effective method to uphold the information security for high-assurance digital circuits. The GLIFT method associates a security label with each data bit and monitors these labels to expose the illegal information flow in the circuit under tracking. However, the label propagation usually consumes a significant area overhead, especially for the multi-level security lattices. This work aims to reduce the area cost of the GLIFT logic to enhance its applicability. A new implementation technique of GLIFT logic of basic gates is proposed by introducing the logic operation 'minus'. A decoupling-encoding technique of the security labels is also proposed to simplify the GLIFT logic. Furthermore, three improved GLIFT schemes are introduced for different scenarios based on these two techniques. These improved schemes are applied to some ISCAS'85 benchmarks. The evaluation results show that the improved schemes only consume 38.90%, 39.84% and 29.16% area of that of the original GLIFT scheme on average, respectively. [ABSTRACT FROM AUTHOR]