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The general model of a phase-change memory (PCM) cell is very complex due to electrical property, thermal transfer and crystal growth. In this paper the general model is equivalent to an RC circuit, via which the dependence of the cell resistance on the number of pulses (Set or Reset) was investigated. Moreover, as for dual-port asynchronous operations of a pore-type PCM cell, a double-capacitor-based cell model was proposed. By simulation on the model we verified feasibility of the cell’s logic and arithmetic operations. In addition, the simulation results of addition and subtraction show that the resistance changes linearly with a short pulse sequence. [ABSTRACT FROM AUTHOR]

Memristive stateful logic has emerged as a promising next-generation in-memory computing paradigm to address escalating computing-performance pressures in traditional von Neumann architecture. Here, we present a nonvolatile reprogrammable logic method that can process data between different rows and columns in a memristive crossbar array based on material implication (IMP) logic. Arbitrary Boolean logic can be executed with a reprogrammable cell containing four memristors in a crossbar array. In the fabricated Ti/HfO2/W memristive array, some fundamental functions, such as universal NAND logic and data transfer, were experimentally implemented. Moreover, using eight memristors in a 2  ×  4 array, a one-bit full adder was theoretically designed and verified by simulation to exhibit the feasibility of our method to accomplish complex computing tasks. In addition, some critical logic-related performances were further discussed, such as the flexibility of data processing, cascading problem and bit error rate. Such a method could be a step forward in developing IMP-based memristive nonvolatile logic for large-scale in-memory computing architecture. [ABSTRACT FROM AUTHOR]

The temperature dependence of crystallization kinetics of phase-change materials raises a series of reliability issues, while phase-change memory cells work at high temperature or thermal-disturbance condition. These issues hinder the development of ultrahigh-density storage devices. We investigate the evolution of SET switching characteristics of phase-change memory cells at high operating temperature. We show that the high temperature strongly impacts the SET state resistance. As a result, SET failure has been observed with elevated ambient temperature. Our SPICE simulations indicate that transient amorphization behavior during a complete SET pulse period is considered as the potential mechanism of SET failure. By modifying the SET pulse intensity and width linearly, we successfully reduce the SET failure in the experiments. The results illustrate that the demonstrated linear properties may optimize SET pulse performance. [ABSTRACT FROM AUTHOR]