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This paper introduces a novel CMOS second-generation current-controlled current conveyor (CCCII) that has a wide tunable intrinsic resistance ( R x ). The designed structure is achieved by the combination of one ordinary CCCII, one cross-coupled OTA and one active resistor. An inverse relationship between the intrinsic resistance and external bias current is created for the first time in CMOS CCCII design, which results in wide tuning range of R x . Performance of the proposed circuit is discussed by detailed analysis. The CMOS CCCII is simulated in TSMC 0.18 μ m RF CMOS technology. The simulation results confirm that the proposed CMOS CCCII achieves a wide tunable R x (from 197.4 Ω to 27.23 k Ω ) while maintaining favorable performance in bandwidth, transfer gain and linear range. In addition, a new reconfigurable structure, which can function as a universal filter or a quadrature oscillator via controlling an enabled switch, is given as an application example to validate the feasibility of the proposed CMOS CCCII. [ABSTRACT FROM AUTHOR]

In this paper, a flux-controlled memristor with linear memductance is proposed. Compared with the memristor with piecewise linear memductance and the memristor with smooth continuous nonlinearity memductance which are widely used in the study of memristive chaotic system, the proposed memristor has simple mathematical model and is easy to implement. Multisim circuit simulation and breadboard experiment are realized, and the memristor can exhibit a pinched hysteresis loop in the voltage-current plane when driven by a periodic voltage. In addition, a new hyper-chaotic system is presented in this paper by adding the proposed memristor into the Lorenz system. The transient chaos and multiple attractors are observed in this memristive system. The dynamical behaviors of the proposed system are analyzed by equilibria, Lyapunov exponents, bifurcation diagram and phase portrait. Finally, an electronic circuit is designed to implement the hyper-chaotic memristive system. [ABSTRACT FROM AUTHOR]

This paper presents a high linearity and low power Low-Noise Amplifier (LNA) for Ultra-Wideband (UWB) receivers based on CHRT 0.18m Complementary Metal-Oxide-Semiconductor (CMOS) technology. In this work, the folded topology is adopted in order to reduce the supply voltage and power consumption. Moreover, a band-pass LC filter is embedded in the folded-cascode circuit to extend bandwidth. The transconductance nonlinearity has a great impact on the whole LNA linearity performance under a low supply voltage. A post-distortion (PD) technique employing an auxiliary transistor is applied in the transconductance stage to improve the linearity. The post-layout simulation results indicate that the proposed LNA achieves a maximum power gain of 12.8dB. The input and output reflection coefficients both are lower than dB over 2.5-11.5GHz. The input third-order intercept point (IIP3) is 5.6dBm at 8GHz and the noise figure (NF) is lower than 4.0dB. The LNA consumes 5.4mW power under a 1V supply voltage. [ABSTRACT FROM AUTHOR]

In this paper, a high gain low voltage low power Complementary Metal Oxide Semiconductor (CMOS) Low-noise Amplifier (LNA) using Chartered 0.18m CMOS process for Ultra-wideband (UWB) receiver applications is presented. A novel multiple-feedback network constructed by the shunt feedback resistor with a transformer is adopted to realize desirable bandwidth extension and less chip area occupation in the common-source stage. All the cascaded transistors are configured by current-reuse structure and adjusted by forward body bias technique to further reduce supply voltage and power dissipation. The post-layout simulation results demonstrate that the proposed 3.4-10.1GHz UWB LNA accomplishes a maximum gain of 14.26dB with only 2.33mW power consumption at 0.8V supply voltage, while Noise Figure (NF) is 1.49-3.41dB and the chip area is 0.46mm2 including test pads (core area is 0.23mm2). [ABSTRACT FROM AUTHOR]