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This paper presents a high linearity and low power Low-Noise Amplifier (LNA) for Ultra-Wideband (UWB) receivers based on CHRT 0.18m Complementary Metal-Oxide-Semiconductor (CMOS) technology. In this work, the folded topology is adopted in order to reduce the supply voltage and power consumption. Moreover, a band-pass LC filter is embedded in the folded-cascode circuit to extend bandwidth. The transconductance nonlinearity has a great impact on the whole LNA linearity performance under a low supply voltage. A post-distortion (PD) technique employing an auxiliary transistor is applied in the transconductance stage to improve the linearity. The post-layout simulation results indicate that the proposed LNA achieves a maximum power gain of 12.8dB. The input and output reflection coefficients both are lower than dB over 2.5-11.5GHz. The input third-order intercept point (IIP3) is 5.6dBm at 8GHz and the noise figure (NF) is lower than 4.0dB. The LNA consumes 5.4mW power under a 1V supply voltage. [ABSTRACT FROM AUTHOR]

In this paper, a high gain low voltage low power Complementary Metal Oxide Semiconductor (CMOS) Low-noise Amplifier (LNA) using Chartered 0.18m CMOS process for Ultra-wideband (UWB) receiver applications is presented. A novel multiple-feedback network constructed by the shunt feedback resistor with a transformer is adopted to realize desirable bandwidth extension and less chip area occupation in the common-source stage. All the cascaded transistors are configured by current-reuse structure and adjusted by forward body bias technique to further reduce supply voltage and power dissipation. The post-layout simulation results demonstrate that the proposed 3.4-10.1GHz UWB LNA accomplishes a maximum gain of 14.26dB with only 2.33mW power consumption at 0.8V supply voltage, while Noise Figure (NF) is 1.49-3.41dB and the chip area is 0.46mm2 including test pads (core area is 0.23mm2). [ABSTRACT FROM AUTHOR]