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In this work, we demonstrated that the 5-nm-thick HfAlO x negative capacitance transistor (NCFET) with optimized Al doping can achieve a minimum 33 mV dec−1 subthreshold swing (SS), an ultralow I off of 7.44 fA μm−1, and a high I on /I off ratio of 1.9 × 108. The NC switching with sub-60 mV dec−1 SS can be implemented from V DS = 0.2 V to 0.8 V due to an ultralow off-state leakage current. The experimental results reveal that well-controlled Al doping in HfAlO x not only reduces off-state leakage of the transistor, but also improves the ferroelectric NC effect to achieve a sub-60 mV dec−1 switching under a favorably low sub-1 voltage. This scaled HfAlO x NCFET with optimized Al doping and fluorine defect passivation shows the great potential for the application of low power logic devices.

We have studied the reliability of high-κ (κ~49) TixHf1-xO (x ~0.67) metal–insulator–metal (MIM) capacitors after constant voltage stress induction. The use of a high-work-function Ni top electrode improves not only the leakage current, and temperature- and voltage-coefficients of capacitance, but also the long-term capacitance variation after stress induction.

High electrostatic discharge (ESD) protection robustness and good transient-induced latchup immunity are two important issues for high voltage integrate circuit application. In this study, we report a high-voltage-n-type-field (HVNF) implantation to act as the body ties blocking layer in segmented topology silicon-controlled-rectifier (SCR) structure in 0.11 µm 32 V high voltage process. This body ties blocking layer eliminate the elevated triggered voltage in segmented technique. Using a large resistance as shunt resistor in resistor assisted triggered SCRs stacking structure, the double snapback phenomenon is eliminate. The series SCR could be decoupled a sufficient voltage drop to turned-on when a very low current flow through the shunt resistor. The holding voltage and the failure current of 22 V and 3.4 A are achieved in the best condition of segmented topology SCR stacking structure, respectively. It improves the latchup immunity at high voltage ICs application. On the other hand, the triggered voltage almost keep the same value which is identical to SCR single cell without using segmented topology.

In this study, we investigate the impact of orientated crystalline InGaZnO (IGZO) thin film transistor. To evaluate interface thermodynamic stability of temperature-sensitive IGZO film, the film-structural stabilities of high- and low-indium-content InGaZnO were studied. With increasing annealing temperature up to 700 °C, the crystallinity becomes more pronounced while device electrical characteristics are further improved. We find that the apparently reduced off-state current can be attributed to the formation of c-axis-orientated crystalline located at the X-ray diffraction peak of . The performance improvements include a very low turn-on voltage close to zero voltage, a small subthreshold swing of 130 mV/dec, and a low off-state current of 2.4 × 10−14 A/µm at a low operating voltage of 4 V.

To meet the requirements of flexible memory applications, we have compared two capping layers of GeOx and AlOx on a TiOy resistive random access memory (RRAM) at room temperature. A Ni/GeOx/TiOy/TaN RRAM shows a large resistance window of >102, 85 °C retention, a high-resistance-state (HRS) activation energy (Ea) of 0.52 eV, and a good DC cycling of 103 cycles, which are significantly better than those of a Ni/AlOx/TiOy/TaN RRAM, which has a high-defect-density dielectric of AlOx.

In this study, we investigate the grain size effect of high electron mobility transistor devices with ohmic contact metals of stacked Ti/Al/Ni/Au and Ti/Al/Mo/Au. In addition to a comparison of electrical characteristics, the ohmic contacts were also examined by a scratch test for the observation of adhesion behavior. The experimental results demonstrate that the metal grain size is strongly dependent on metal adhesion, which may lead to bonding issues. Moreover, the grain-induced lateral stress lowers the drive current and increases the off-state current owing to the degraded gate swing and transconductance of transistor switching characteristics.

In this study we propose a resistive random-access memory (RRAM) using stacked GeO x and PbZr0.5Ti0.5O3 (PZT). Under unipolar-mode operation, the bilayers Ni/GeO x /PZT/TaN RRAM shows a large resistance window of >102, for 85 °C retention, and a good DC cycling of 2000 cycles, which are significantly better than those shown by the single-layer Ni/PZT/TaN RRAM without the covalent-bond-dielectric GeO x .

The effect of Ta2O5 doping on electrical characteristics of SrTiO3 (STO) metal–insulator–metal (MIM) capacitors was studied for the first time. Using Ta2O5-doped STO dielectrics, an absolute quadratic voltage coefficient of capacitance (VCC-α) of 510 ppm/V2 and a high capacitance density of ~20 fF/µm2 are achieved. These are approximately one order of magnitude lower than those of the MIM capacitor fabricated using a pure STO. In addition, the degradation of electrical properties (capacitance variation versus voltage, VCC-α, and long-term reliability) after electrical stressing is reduced, compared with that of an MIM capacitor fabricated using a pure STO.

Effects of Ni silicidation on the samples that form shallow p+n junctions by BF2 + implantation into thin polycrystalline-Si films on Si substrates have been studied. The pre-formed junctions of the pre-annealed samples are slightly improved as a post Ni silicidation is applied to them, since silicidation can enhance the dopant diffusion. A silicided junction with a leakage of about 1 nA/cm2 at -5 V is obtained by the sample pre-annealed at 800°C and post NiSi-silicided at 600°C. On the other hand, as the samples are treated by depositing thin Ni films just after the implantation and then annealing, the resulting junctions are much better than the above pre-formed ones, without deepening the junction. During annealing, the simultaneous presence of both the driving forces arising from the Si interstitial and the Ni silicidation would significantly enhance the dopant drive-in efficiency. As a result, an NiSi-silicided shallow junction with a leakage of about 0.8 nA/cm2 and an ideality factor of about 1.00 can be obtained even at 700°C.

A new complete and analytical drain current model for symmetric double-gate silicon-on-insulator metal-oxide-semiconductor field-effect-transistors (SOI MOSFETs) is presented. The model applicable for digital/analog circuit simulation contains the following advanced features: precise description of the subthreshold, near threshold and above-threshold regions of operation by one single expression; considering the source/drain resistance; inclusion of important short channel effects such as velocity saturation, drain induced barrier lowering and channel length modulation; self-heating effect due to the low thermal conductivity of the buried oxide; impact-ionization of MOS devices and parasitic bipolar junction transistor associated with drain breakdown. It was developed using a quasi-two-dimensional Poisson equation.

In this paper we present a new analytical physics-based drain current model for fully overlapped and partially overlapped lightly-doped-drain metal-oxide-semiconductor field-effect-transistors (LDD MOSFETs). The model was developed by starting from a two-dimensional Poisson equation, and including the effects of series resistances and velocity saturation. In particular the phenomenon of surface accumulation and depletion in the LDD region is included in the model to describe saturation I–V characteristics. The device is partitioned into the source, intrinsic channel, subdiffusion, and overlapped and non-overlapped lightly-doped drain regions. The device parameters such as local threshold voltage and doping concentration are continuous along the channel. The model can describe the I–V characteristics and can be used to calculate the electric fields in the channel region and in the LDD region for the device operated in both the linear and saturation regions. The accuracy of the presented model has been verified by the simulated data using a fully numerical 2D simulator and the experimental data of LDD devices with various geometries.

This paper presents a simple, complete, and analytical drain current model for submicrometer silicon-on-insulator metal-oxide-semiconductor field-effect-transistor (SOI MOSFET). The model applicable for digital/analog circuit simulation contains the following advanced features: precise description of the subthreshold, near threshold, and above-threshold regions of operation by one single expression; precise description of I–V and G–V characteristics in the saturation region; single-piece drain current equation smoothly continuous from the linear region to saturation region; considering the source/drain resistance; inclusion of important short channel effects such as velocity saturation, drain induced barrier lowering and channel length modulation; self-heating effect due to the low thermal conductivity of the buried oxide; impact-ionization of MOS devices and the parasitic bipolar junction transistor (BJT) effect associated with drain breakdown. The model predicts that the parasitic resistances are important for submicron and deep submicron SOI MOS devices, the effects of impact-ionization and parasitic BJT are important in saturation region at small gate source voltage V GF, and self-heating effect is important in saturation region at large V GF. The present model agrees well with experimental results of various dimensions.