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Modeling attacks such as machine learning attacks are pretty efficient in breaking hardware security primitives like silicon strong physical unclonable functions (PUFs). As compared to regular strong PUFs such as arbiter PUFs and lightweight (LW)-PUFs, subthreshold current array (SCA)-PUFs exhibit a better resilience against modeling attacks since they utilize the non-linear relationship between the subthreshold current and gate voltage of transistors to obfuscate the corresponding relationship between input challenge and output response. Unfortunately, the degree of non-linearity (DoNL) within SCA-PUFs is still not sufficiently high to resist against state-of-the-art modeling attacks. Therefore, to further enhance DoNL for resisting against modeling attacks, a new strong PUF architecture is proposed in this paper by embedding reconfigurable neural networks (RNNs) into SCA-PUFs. Mathematical foundations are established for finding appropriate RNNs that are able to maximize the DoNL of an SCA-PUF. As shown in the result, when state-of-the-art modeling attacks like Lagrange multiplier attacks (LMAs) are selected, the robustness of the proposed RNN-embedded SCA-PUF is enhanced over 20 times with less than 18.5% power and area overhead as compared to a regular SCA-PUF. • SCA-PUF utilizes the non-linear sunthreshold current of transistors. • SCA-PUF is quite vulnerable to advanced modeling attacks such as LMAs. • RNN-embedded SCA PUF resists LMAs by masking power side-channel information. [ABSTRACT FROM AUTHOR]

With the Integrated Circuits becoming pervasive in all key industries and applications, PUF's has gained immense popularity for securing the IC's by providing unique identification code to each chip. Designing a highly efficient PUF with optimal values of uniqueness and reliability is a significant challenge. Uniqueness depends on process variations during chip fabrication, and reliability depends on the chip's ability to resist changes to supply voltage and temperature variations. Multiple PUF designs that employ reliability enhancement circuits and security algorithms achieve these design characteristics. Nonetheless, these techniques are design overheads. This paper presents a novel Physical Unclonable Function (PUF) based on the ProHys switch. It deals with hysteresis and proteresis mode of operation, which are complementary to each other. The Prohys PUF befittingly satisfies both uniqueness and reliability criteria, without any additional circuitry or security algorithms. It is the first attempt to design a PUF based on the ProHys switch to the best of our knowledge. The proposed ProHys PUF is designed in TSMC 180 nm CMOS technology, generating an inter-chip variation of 49.85% with 99.7% uniqueness. The minimum reliability of the circuit is 96.9% for a temperature range of -40 °C to 100 °C at a supply voltage range of 1.7V–1.9V. • A novel Physical Unclonable Function (PUF) based on ProHys switch is presented. • It satisfies uniqueness and reliability criteria without any additional circuitry. • This is the first attempt to design a ProHys based PUF, to the best of our knowledge. • Proposed PUF generates an inter-chip variation of 49.85% and uniqueness of 99.7%. • The minimum circuit reliability is 96.9% at a supply voltage range of 1.7 V–1.9 V. [ABSTRACT FROM AUTHOR]

Various security measures for IoT devices have been introduced in recent years. One of the improvements is through the addition of cryptographic hardware along with the central core processor. As IoT devices are resource-constrained, area and power-efficient solutions are needed. Every cryptographic algorithm has a key generator that provides proper keys to encrypt and decrypt the data. This paper focuses on improving the key generators using Physical Unclonable Functions (PUFs). Execution of NIST-STS randomness test and evaluation of crucial performance parameters is done for the generated bit-stream by proposed PUF design. The proposed design is also compared with three designs from the literature based on area and power consumption which are essential parameters for resource-constrained IoT devices. For proposed design number of LUTs, FFs and power consumption are decreased up to 80%, 76% and 67%, respectively, when implemented on Xilinx Artix-7 FPGAs. • PUF based approach to be used for key generation. • A comparative study is done with RO, TERO, and Arbiter PUF. • The output bitstream of the proposed design also checked for randomness, entropy, uniqueness, steadiness, uniformity, and bit-aliasing. • Efficient key generator design for the cryptographic algorithm in terms of area and power consumption is identified as PDL-PUF based design. [ABSTRACT FROM AUTHOR]

In the field of hardware security, the physical unclonable function (PUF) is known as a significant advancement for its unique and unclonable outputs, serving as a 'digital fingerprint' for electronic devices. This distinctiveness is crucial for high-security tasks such as device authentication and cryptographic key generation. The PUF's input-output combinations, known as challenge-response pairs (CRPs), are essential to its functionality. Although the Ring Oscillator (RO) PUF is notable for its security advantages and straightforward implementation, it's considered a 'weak' PUF due to its limited CRPs, highlighting a demand for more robust and secure PUF designs. This paper introduces a novel configurable inversion unit (CIU), integrating two universal logic gates, NAND and NOR, to be utilized in building various configurable ring oscillator (CRO) PUF models. Using the newly proposed CIU, we introduce two distinct CRO-PUF configurations. The first one includes 16-ring oscillators, while the second has 8-ring oscillators. A modified version of this CIU is introduced to increase the size of CRPs that a PUF can handle. A comprehensive assessment process of these configurations underscores the superior performance of these models across various parameters, including reliability, distinctiveness, balance, bit-aliasing, and randomness. • MUX-based CRO PUFs mainly utilize inverters and XOR gates. • XOR gates in CRO-PUFs, with/without MUXs, boost RO-PUF efficacy. • Few CRO-PUF designs use NAND/NOR universal gates. • More ring oscillators in PUFs link to better security. [ABSTRACT FROM AUTHOR]

Silicon Physical unclonable functions (PUFs) are regarded as emerging hardware security primitives that can be used for generating secret keys for cryptographic algorithms. Unfortunately, the reliability issues greatly limit the applications of most PUFs since ambient noises and aging issues may alter the output responses of the PUFs. In this paper, a novel error calibration technique (ECT) based on average sampling circuit (ASC) and self-checking circuit (SCC) is proposed for significantly boosting the reliability of PUFs. The primary role of ASC is filtering the ambient noises that may affect the output responses of the PUFs. In contrast, SCC rehabilitates the PUFs once aging issues damage the process mismatches within the PUFs. As shown in the result, a PUF with the proposed ECT is able to achieve a 99% reliability with a 50 Mbps throughput. • Regular PUFs have poor reliability issues due to the effects of ambient noises and aging issues. • Error calibration technique (ECT) is able to the improve the corresponding reliability significantly by filtering critical noises. • An ECT-based PUF offers a high throughput without causing much area overhead. [ABSTRACT FROM AUTHOR]

Physically Unclonable Functions (PUFs) are a promising technology and have been proposed as central building blocks in many cryptographic protocols and security architectures. Among other uses, PUFs enable chip identifier/authentication, secret key generation/storage, seed for a random number generator and Intellectual Property (IP) protection. Field Programmable Gate Arrays (FPGAs) are re-configurable hardware systems which have emerged as an interesting trade-off between the versatility of standard microprocessors and the efficiency of Application Specific Integrated Circuits (ASICs). In FPGA devices, PUFs may be instantiated directly from FPGA fabric components in order to exploit the propagation delay differences of signals caused by manufacturing process variations. PUF technology can protect the individual FPGA IP cores with less overhead. In this article, we first provide an extensive survey on the current state-of-the-art of FPGA based PUFs. Then, we provide a detailed performance evaluation result for several FPGA based PUF designs and their comparisons. Subsequently, we briefly report on some of the known attacks on FPGA based PUFs and the corresponding countermeasures. Finally, we conclude with a brief overview of the FPGA based PUF application scenarios and future research directions. [ABSTRACT FROM AUTHOR]

With the development of system-on-chip (SoC) chips, more and more design houses are cooperating with each other's. How to achieve benefit sharing and key management for multiple intellectual properties (IPs) has become an emergency problem. This work proposes an orthogonal obfuscation method to protect multiple IPs. The proposed method permits cooperators to control the project using different security keys, protects the patterns with an orthogonal key, and be convenient for the user to manage the key. For reasons of increased security, the proposed method hides the original keys to prevent information leakage. Multi-port Physical Unclonable Function (MPUF) circuit is used as the additional orthogonal key to cluster membership. It protects the IPs from hardware attacks such as brute-force attack, member leakage attack, reverse engineering and so on. The security analyzes results show that the proposed method reduces the key retrieval time by 36.3% over the baseline. The proposed obfuscation methods have been successfully applied to ISCAS′89 benchmark circuits and cryptographic algorithms. Experimental results indicate that the orthogonal obfuscation only increases the area by 3.43% and consumes 2.77% more power than the baseline. • We proposed hardware obfuscation method using an algebraic orthogonal functionality to authenticate for multiple IPs. The orthogonal method permits cooperators to control the project using different security keys, which is different from the key managed by the leader. • The proposed orthogonal obfuscation is not limited to linear algebra, but also IC design. Moreover, the security of the presented method against various attacks is discussed, such as brute-force attack, member leakage attack, reverse engineering and side channel attacks, and so on. • MPUF circuit selects multiple orthogonal vectors as the key of cluster membership. The obfuscation of MPUF allows the user to determine whether the input point is on the orthogonal. [ABSTRACT FROM AUTHOR]