FPGA implementation of PUF based key generator for secure communication in IoT.

Various security measures for IoT devices have been introduced in recent years. One of the improvements is through the addition of cryptographic hardware along with the central core processor. As IoT devices are resource-constrained, area and power-efficient solutions are needed. Every cryptographic algorithm has a key generator that provides proper keys to encrypt and decrypt the data. This paper focuses on improving the key generators using Physical Unclonable Functions (PUFs). Execution of NIST-STS randomness test and evaluation of crucial performance parameters is done for the generated bit-stream by proposed PUF design. The proposed design is also compared with three designs from the literature based on area and power consumption which are essential parameters for resource-constrained IoT devices. For proposed design number of LUTs, FFs and power consumption are decreased up to 80%, 76% and 67%, respectively, when implemented on Xilinx Artix-7 FPGAs. • PUF based approach to be used for key generation. • A comparative study is done with RO, TERO, and Arbiter PUF. • The output bitstream of the proposed design also checked for randomness, entropy, uniqueness, steadiness, uniformity, and bit-aliasing. • Efficient key generator design for the cryptographic algorithm in terms of area and power consumption is identified as PDL-PUF based design. [ABSTRACT FROM AUTHOR]