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Mixed-signal components, such as low dropouts (LDOs) and phase locked loops (PLLs), are widely used inside the on-chip power management fabric of low power integrated system-on-chip (SoC) designs. The digital brain of the power management logic that is responsible for regulating the power delivery to different power domains in the chip has to consider the real time latencies of the analog components, which otherwise leads to functional errors in the domains being driven. The latencies may be viewed as contracts between the digital and the analog. This article presents an approach for generating assertions for protecting such mixed-signal latency contracts and using them to rule out timing bugs in the power management logic. Our tool flow enables the verification of the power management fabric, combining a novel mixed-signal assertion checking method in a simulation setting, and a full formal verification method for the digital brain of the power management logic. To the best of our knowledge, this is the first framework where assertions are used for binding analog latency contracts on the digital logic of power management. [ABSTRACT FROM AUTHOR]

This paper presents a switching scheme-based placement method to reduce the effect of various sources of nonlinearity arising due to layout routing parasitic in a current-steering digital-to-analog converter (DAC), thereby providing excellent static and dynamic performance. The proposed technique reduces both the individual and the cumulative effect of different nonidealities. Improvement in both the static and the dynamic performance is observed when compared with that provided by conventional common centroid placement. A 10-bit 500-MHz differential current-steering DAC has been designed and evaluated in 65-nm CMOS process as a case study, which provides a $\sim 72$ -dB spurious-free dynamic range at a 122-Ms/s input frequency. [ABSTRACT FROM PUBLISHER]

Noise, especially clock jitter effects, in a DSP-based mixed-signal test system severely limits its measurement accuracy. This is especially acute in high-frequency sampling systems. This paper illustrates an efficient method to improve measurement accuracy and precision by reducing the uncertainty of a DSP-based measurement without an increase in test time. A new digitizer architecture is introduced. The digitizer was fabricated in a 0.18-pm CMOS process. Experimental results were obtained validating the proposed technique. [ABSTRACT FROM AUTHOR]