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We use ac and dc Technology Computer Assisted Design simulations to study the effects of radiation damage in the planar pixel sensors of the ATLAS inner detector upgrade, in particular on the active area and breakdown protection of different multiguard rings structure. Using a model of defect introduction into silicon band gap that agrees well with simulation up to fluences of 1015neq /cm², we simulated how high radiation damage phenomena like space-charge sign inversion and double-junction formation affects the efficiency of different models of multiguard ring structures in n-type and p-type bulk. Depletion potential, potential distribution on guard rings, breakdown voltage, and leakage current were extracted from simulations to compare the behavior of the different models. [ABSTRACT FROM AUTHOR]

We report on n-channel Junction Field Effect Transistors fabricated on high resistivity silicon by means of a specially tailored radiation detector technology. This research activity is being carried out in the framework of a project aiming at the integration of read-out circuits in the same detector substrate. Possible applications are in the field of medical/industrial imaging, space and high energy physics experiments. The pre-existent fabrication process has been modified in several respects to enhance the device noise behavior. In particular, the new process features a high-energy (1 MeV) Boron implantation to obtain a deep p-well which ensures an effective isolation of the transistor from the substrate and a strong modulating effect on the current. Selected results from the experimental characterization of transistors and charge sensitive amplifiers are presented, showing a sizable enhancement in the noise performance with respect to previously available devices. [ABSTRACT FROM AUTHOR]

We describe a methodology to study and select JFET transistors, to be adopted for the readout of bolometric detectors, which makes use of a novel instrument capable of doing very accurate automatic noise measurements at low frequency. Clever design criteria and properly selected biasing conditions allow outstanding results in terms of noise and power dissipation. Noise was explored at very small power dissipation, 2.5 μW, and JFET transistors were biased in a nonconventional region at low temperature. [ABSTRACT FROM AUTHOR]