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Single and multiple-event upsets in \ HfO_2/\ Hf one transistor, one resistor (1T1R) resistive random access memory (RRAM) structures are modeled dynamically using 3-D technology computer-aided design (TCAD) simulations. A dynamic single-event compact model is presented that allows direct correlation of the ion-generated voltage transient across the RRAM and the change in RRAM resistance. Experiments and modeling demonstrate an exponential relationship between the susceptibility of the RRAM and the applied voltage. Two implementations of the model are also presented including hardening voltage-susceptible resistive memory technologies and the impact of highly scaled access transistors. [ABSTRACT FROM PUBLISHER]

We have investigated the effects of biased and unbiased X-ray irradiation on the subsequent time-dependent dielectric breakdown (TDDB) of 130-nm MOSFETs irradiated up to 1 Mrad(SiO2). We found a small but measurable increase in TDDB lifetime after irradiation at the worst-case irradiation bias. The influence of radiation bias on subsequent TDDB is more significant in the PMOSFETs than the NMOSFETs. The increased TDDB lifetime and the irradiation-bias dependence are attributed to the influence of radiation-induced traps on the stressing current during the reliability testing. [ABSTRACT FROM AUTHOR]

The radiation response of complementary metal–oxide–semiconductor (CMOS) gate oxides is typically insensitive to true dose-rate effects, but damage in deep-sub-micrometer technologies is dominated by ionization mechanisms in thick isolation oxides surrounding the transistors. Recent results in 65-nm FETs demonstrated that performance degradation in ultrahigh total ionizing dose (TID) experiments is due to defects in the isolation shallow trench isolation oxide or in the materials composing the lightly doped drain spacers. These insulators are thick, deposited, and crossed by a low electric field, characteristics similar to those typical of passivation oxides in linear bipolar technologies for which an enhanced low-dose-rate sensitivity (ELDRS) has been observed and systematically studied. We report in this paper the clear evidence of a dose-rate sensitivity of the TID-induced damage in both 130- and 65-nm CMOS technologies exposed to different radiation sources (X-rays and $\gamma $ -rays from a 60Co source). This sensitivity is attributed to mechanisms similar to those explaining ELDRS in bipolar devices and represents a significant challenge to the definition of a qualification procedure for circuits to be used in extreme radiation environments. [ABSTRACT FROM AUTHOR]

We demonstrate the utility of focused, pulsed X-rays for investigating localized total ionizing dose effects in bipolar analog integrated circuits. Using the LM139 comparator as a test vehicle, we show how the technique can be used to identify the sources of degradation as a result of irradiating different transistors of the device and how this impacts the input bias current, input offset voltage, and output voltage. The 2-D mapping of the sensitive regions of transistors is presented, where the results of localized irradiation impact the monitored operational parameters. [ABSTRACT FROM PUBLISHER]

The single-event-transient response of InGaAs MOSFETs exposed to heavy-ion and laser irradiations is investigated. The large barrier between the gate oxide and semiconductor regions effectively suppresses the gate transients compared with other types of III-V FETs. After the initial radiation-induced pulse, electrons and holes flood into the channel region at short time. The electrons are collected efficiently at the drain. The slower moving holes accumulate in the channel and source access region and modulate the source-channel barrier, which provides a pathway for transient source-to-drain current lasting for a few nanoseconds. The peak drain transient current reaches its maximum when the gate bias is near threshold and decreases considerably toward inversion and slightly toward depletion and accumulation. Two-dimensional TCAD simulations are used to understand the charge collection mechanisms. [ABSTRACT FROM PUBLISHER]

The total-dose radiation tolerance of 32-nm nFETs is investigated. nFETs built in 32-nm RF-CMOS-on-SOI technology with high-k dielectrics show increased off-state leakage current and electron trapping in the gate oxide. The impact of CMOS-on-SOI technology scaling (from 65-nm to 32-nm) on the total-dose radiation tolerance and hot-carrier reliability (HCR) is investigated through both experiments and supporting TCAD simulations. The 32-nm nFETs exhibit less total-dose degradation compared to 45-nm nFETs. However, the hot-carrier degradation increases as the technology scales. An interplay of electric-field in the gate oxide and impact ionization in the channel region is responsible for the observed differences in the degradation mechanisms for the three technologies. [ABSTRACT FROM AUTHOR]

We have characterized the total ionizing dose (TID) response of SOI FinFETs, fabricated in two different technologies, operated in 1T-DRAM mode, one with poly-crystalline Si gates and a SiO2 gate dielectric, and the other with metal gates and a high-K gate dielectric. These devices were programmed using both back-gate pulse and gate induced drain leakage (GIDL) programming methods. 1T-DRAM cells programmed with back-gate pulses are quite sensitive to total ionizing dose radiation, with the memory sensing margin and retention time decreasing significantly with increasing dose. In contrast, the sensing margin and retention time show high tolerance to total ionizing dose irradiation when the 1T-DRAM cells are programmed via GIDL. The sensing margin increases significantly with decreasing gate length for 1T-DRAM cells programmed via GIDL. We conclude that capacitor-less 1T-DRAMs programmed via GIDL are strong candidates for embedded memory applications for ultimately scaled CMOS devices in high-TID applications. [ABSTRACT FROM AUTHOR]

Proton and X-ray irradiation effects are investigated in 0.35 µm conventional, annular, and ringed-source radiation-hardening-by-design (RHBD) CMOS devices. Transistors were irradiated with protons at both 300 K and 77 K. Radiation-induced oxide trapped charges in the shallow trench isolation (STI) oxide deplete the p-substrate and effectively shunt the source and drain, inducing off-state leakage. Without the STI, RHBD nFETs exhibit no radiation-induced off-state shunt leakage currents for devices irradiated at both 300 K and 77 K. Conventional 0.35 µm pFETs were not degraded by proton irradiation, since the leakage path cannot be formed in the n-well. A simple CMOS logic inverter shows no degradation in output voltage after proton irradiation for all tested temperature and bias conditions. More advanced 130 nm node nFETs show less TID sensitivity to STI leakage due possibly to the smaller physical STI volume and/or additional doping located on the STI sidewall. [ABSTRACT FROM AUTHOR]