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In the mm-wave frequency band, the rectifier’s sensitivity is the bottleneck of a wireless-powered IoT transponder’s distance. At a meter’s distance, the received power is weak, and transistors in a front end of a wireless power receiver operate in the weak inversion region. This article presents a mathematical analysis of the mm-wave multi-stage rectifier in the low-power region. A design methodology of a 57–64-GHz fully integrated eight-stage rectifier with a bulk-drain connection in 40-nm CMOS technology is presented. Parasitic effects on a multi-stage rectifier are analyzed. Based on the analysis, an intrinsic threshold voltage modulation is applied to improve the sensitivity. A tree-type power splitter is also proposed for the RF power signal’s phase balance. With this method, the RF signal arrives at each stage with an equal phase, and its suppression at the output is improved by 16 dB. This mm-wave rectifier achieves −7.1-dBm input sensitivity at 57 GHz with 1-V dc output voltage. The overall sensitivity from 57 to 64 GHz is better than −4.5 dBm. Compared to other mm-wave silicon-based rectifier state of the arts, the proposed mm-wave rectifier achieves better sensitivity while maintaining a compact size. [ABSTRACT FROM AUTHOR]

This research work presents the analysis, design, and characterization of a concept for an mm-wave divide-by-4 frequency divider utilizing an extended true single-phase clock (E-TSPC) and a TSPC divide-by-2 stage. The divider operates from 16 to 70 GHz from a 0.8-V supply with the highest power consumption of 0.35 mW. Operating frequencies up to 53 GHz were reached with a supply voltage of only 0.5 V at 0.12-mW power consumption. The self-resonance frequency of the circuit is adjustable through backgate biasing from 40 up to 70 GHz at 0.9-V supply, allowing a reduction in the required input power in this frequency range. Locking ranges up to 114% have been measured by changing only the backgate voltage. The circuit design is illustrated in detail and supported with original analysis and an explicit expression to calculate the self-oscillation frequency of the E-TSPC divider. The presented circuit was fabricated on a 22-nm fully depleted silicon-on-isolator complementary metal–oxide–semiconductor (CMOS) technology and occupies an active area of $3.4 ~\mu \text{m}^{2}$. The circuit requires the lowest power consumption and area among state-of-the-art RF frequency dividers, while it demonstrates the second widest adjustable operating frequency range and the second highest self-resonance frequency for CMOS D-flip-flop frequency dividers. [ABSTRACT FROM AUTHOR]

This article presents a reflectometer-based on-chip dielectric sensor with integrated transducers at 240 GHz. The chip simplifies the measurement of a vector network analyzer (VNA) to sense the incident and reflected waves by using two heterodyne mixer-based receivers with a dielectric sensing element. Radio frequency (RF) and local oscillator (LO) submillimeter waves are generated by two frequency multiplier chains, respectively. Two back-to-back identical differential side-coupled directive couplers are proposed to separate the incident and reflected signals and couple them to mixers. Both transmission line and coplanar stripline transducers are proposed and integrated with reflectometer to investigate the sensitivity of dielectric sensors. The latter leads to a larger power variation of the reflectometer by providing more sufficient operating bands for the magnitude and phase slope of $S_{11}$. The readout of the transducers upon exposure to liquids is performed by the measurement of their reflected signals using two external excitation sources. The experimental dielectric sensing is demonstrated by using binary methanol–ethanol mixture placed on the proposed on-chip dielectric sensor in the assembled printed circuit board. It enables a maximum 8 dB of the power difference between the incident and reflected channels on the measurement of liquid solvents. Both chips occupy an area of 4.03 mm2 and consume 560 mW. Along with a wide operational frequency range from 200 to 240 GHz, this simplified one-port-VNA-based on-chip device makes it feasible for the use of handle product and suitable for the submillimeter-wave dielectric spectroscopy applications. [ABSTRACT FROM AUTHOR]

In this article, a 60-GHz frequency-modulated continuous-wave (FMCW) multiple-input multiple-output (MIMO) radar system using frequency-division multiplexing for TX signal separation is presented. Four-channel transmitter and receiver chips were designed using 130 nm SiGe process. The total number of TX and RX channels can be scaled by the number of chips in the system while still maintaining phase coherence between the channels. 2-D and 3-D object localization measurements are made with four TX and eight RX channel systems. In the 2-D configuration, the radar system is capable of a 5-cm range resolution and 3.5° angular resolution. [ABSTRACT FROM AUTHOR]

In this paper, a novel direct learning algorithm is proposed to identify the digital predistortion (DPD) coefficients that linearize a power amplifier (PA) using sub-Nyquist sampled intermediate frequency (IF) output of a heterodyne transmitter observation receiver (TOR). The learning algorithm is complemented with a joint time and phase alignment procedure to compensate for the unknown phase of the IF carrier as well as the delay between the PA input and output signals. By sub-Nyquist sampling at IF, the proposed method avoids the need for challenging receiver calibration that compensates for significant IQ imbalance exhibited by direct conversion receivers. Furthermore, it provides a very attractive flexibility in choosing the IF and consequently allows for a high subsampling factor. It is also extended to account for the nonflat frequency response of the TOR, thus avoiding the need for an explicit calibration step. Finally, measurement results were performed to linearize a PA demonstrator driven by a 320-MHz wide carrier aggregated LTE signal centered at 31 GHz using a complexity reduced Volterra-based DPD. Excellent linearization capacity (ACPR of 50 dBc and normalized mean square error of 2%) using significantly low sampling rates (as low as 40 Msps) is reported. [ABSTRACT FROM AUTHOR]

This paper presents a monitoring and control system for MEMS tunable evanescent-mode cavity filters. Inductive proximity sensing is utilized to detect the deflection of the tuning MEMS membrane. The sensed deflection is used as a feedback for a closed-loop control of the MEMS bias voltage to deliver the desired deflection and, hence, desired RF response based on an input from the user. The sensing spiral inductor also functions as an electrode for the electrostatic actuation of the membrane. The presented system is analyzed, optimized, and experimentally implemented on a bandstop filter tunable in the 30–42-GHz range. The measured results show that the system is capable of tuning the filter to the desired response with good repeatability of notch frequency (less than 1% error) and with stable long-term response (better than 1.6% drift), which falls within the 20-dB bandwidth of the filter. [ABSTRACT FROM AUTHOR]

This paper presents a 64-element 28-GHz phased-array transceiver for 5G communications based on $2\times 2$ transmit/ receive (TRX) beamformer chips. Sixteen of the $2\times 2$ TRX chips are assembled on a 12-layer printed circuit board (PCB) together with a Wilkinson combiner/divider network and 28–32-GHz stacked-patch antennas. The 64-element array results in 1.1 dB and 8.9° rms amplitude and phase error, respectively, with no calibration due to the symmetric design of the $2\times 2$ beamformer chips and the PCB Wilkinson network. The effect of phase and amplitude mismatch between the 64 elements is analyzed and shown to have little impact on the 64-element array performance due to the averaging effects of phased arrays. Detailed pattern, effective isotropic radiated power (EIRP), and link measurements performed without any array calibration are presented and show the robustness of the symmetrical design technique. The phased array can scan to ±50° in azimuth ($H$ -plane) and ±25° in elevation ($E$ -plane) with low sidelobes and achieves a saturated EIRP of 52 dBm with 4-GHz 3-dB bandwidth. A 300-m wireless link is demonstrated with a record-setting data rate of 8–12 Gb/s over all scan angles using two 64-element TRX arrays and 16-/64-QAM waveforms. [ABSTRACT FROM AUTHOR]

This paper presents the first wirelessly synchronized multichip array (WSMA) in 65-nm CMOS. The proposed architecture makes use of a central wireless signal to synchronize an mm-wave array, eliminating the need for connecting wires between the array elements. Wireless injection locking of a single chip is successfully demonstrated, and a 3-dB linewidth of 400 Hz at a carrier frequency of 50 GHz is achieved (stability ratio of 8 ppb). In addition, a two-element WSMA with an array aperture greater than 20 wavelengths is demonstrated using the proposed transceiver architecture. The reported transceiver includes a receiving on-chip antenna, a low-noise amplifier, an injection-locked voltage-controlled oscillator, a buffer amplifier, an in-phase/quadrature generator, a phase shifter, a power amplifier, and a transmitting on-chip antenna. The chip is fabricated in a 65-nm CMOS process and occupies an area of 1.7 mm $\times 3.8$ mm. This paper sets the foundation for increasing the array aperture through wireless injection locking, extending traditional array systems into the high-resolution, narrow-beamwidth regime. [ABSTRACT FROM PUBLISHER]

Although wireless sensor networks (WSNs) have been an active field of research for many years, the modules incorporated by WSN nodes have been mainly manufactured utilizing conventional fabrication techniques that are mostly subtractive, requiring significant amounts of materials and increased chemical waste. The new era of the Internet of Things (IoT) will see the fabrication of numerous small form factor devices for wireless sensing for a plurality of applications, including security, health, and environmental monitoring. The large volume of these devices will require new directions in terms of manufacturing cost and energy efficiency, which will be achieved with redesigned, energy-aware modules. This paper presents the state of the art of printed passives, sensors, energy harvesting modules, actives, and communication front ends, and summarizes the challenges of implementing modules that feature low power consumptions without compromising the low fabrication cost. The plethora of the modules presented herein will facilitate the implementation of low cost, additively manufactured, energy-aware IoT nodes that can be fabricated in large volumes with green processes. [ABSTRACT FROM AUTHOR]

This paper presents a CMOS amplifier-multiplier-antenna array capable of generating an EIRP of 3–4 dBm at 420 GHz. The chip is built using a 45-nm CMOS SOI process, and efficient on-chip antennas are used to extract the power out of the chip. The design is based on a 90–110 GHz distribution network with splitters and amplifiers, and a balanced quadrupler capable of delivering up > \100~\mu\W of power at 370–430 GHz. The amplifier–multiplier concept is proven on a 2\times4 array, and it can be also scaled to any N\times M array using additional W-band splitters and amplifiers. [ABSTRACT FROM AUTHOR]

This paper presents a novel design of cylindrical modified Luneberg lens antenna at millimeter-wave (mm-wave) frequencies in which no dielectric is needed as lens material. The cylindrical modified Luneberg lens consists of two air-filled, almost-parallel plates whose spacing continuously varies with the radius to simulate the general Luneberg's Law. A planar antipodal linearly-tapered slot antenna (ALTSA) is placed between the parallel plates at the focal position of the lens as a feed antenna. A combined ray-optics/diffraction method and CST-MWS are used to analyze and design this lens antenna. Measured results of a fabricated cylindrical modified Luneberg lens with a diameter of 100 mm show good agreement with theoretical predictions. At the design frequency of 30 GHz, the measured 3-dB E- and H-plane beamwidths are 8.6^\circ and 68^\circ, respectively. The first sidelobe level in the E-plane is - 20~dB, and the cross-polarization is - 28~dB below peak. The measured aperture efficiency is 68% at 30 GHz, and varies between 50% and 71% over the tested frequency band of 29–32 GHz. Due to its rotational symmetry, this lens can be used to launch multiple beams by implementing an arc array of planar ALTSA elements at the periphery of the lens. A 21-element antenna array with a - 3\mathchar"702D dB beam crossover and a scan angle of 180^\circ is demonstrated. The measured overall scan coverage is up to \pm80^\circ with gain drop less than - 3~dB. [ABSTRACT FROM AUTHOR]

This paper presents an ultrafast wideband low-loss single-pole double-throw (SPDT) differential switch in 0.35 \mum SiGe bipolar technology. The proposed topology adopting current-steering technique results in a total measured switching time of 75 ps , which suggests a maximum switching rate of 13 Gb/s, the fastest ever reported at V-band. In addition, the switch exhibits an insertion loss lower than 1.25 dB and an isolation higher than 18 dB from 42 GHz to 70 GHz. [ABSTRACT FROM AUTHOR]