Search

Stacked nanosheet nFETs considering a six-stack four-finger transistor array are studied and optimized by validated TCAD simulation. Stacked Si nanosheet (NS) nFETs have lower parasitics than nFinFETs in the same six-fin/stack four-finger transistor array layout. With the same electron mobility, back-end-of-line (BEOL), equivalent oxide thickness (EOT) of 1.4 nm, and gate length of 30 nm, the stacked Si NSs have $1.1\times $ cut-off frequency (240 versus 215 GHz) and $1.15\times $ maximum oscillation frequency (290 versus 251 GHz) when compared to FinFETs due to larger transconductance increase than capacitance increase and output conductance decrease. With the optimized EOT of 0.8 nm and gate length of 18 nm, the stacked Si NSs can achieve cut-off frequency of 340 GHz and maximum oscillation frequency of 370 GHz. Furthermore, considering the higher electron mobility on {100} surfaces of NSs than {110} sidewalls of FinFETs as suggested by the ${I} _{D}$ – ${V}_{\text {GS}}$ fitting, the cut-off frequency and maximum oscillation frequency of stacked Si NSs can reach 380 and 390 GHz, respectively. [ABSTRACT FROM AUTHOR]

This article reports on the extraction of the electron velocity as a function of gate bias from N-polar GaN deep recess high-electron-mobility transistors (HEMTs) designed for mm-wave power amplification. Bias-dependent small-signal S-parameter measurements are used to obtain small-signal equivalent circuit parameters, which are applied to a transit delay model. The model accounts for fringing capacitance to arrive at an electron velocity associated with the transit of the physical gate length. A peak electron velocity of 1.4 × 107 cm/s was obtained at a drain current of 700 mA/mm corresponding to a channel charge density of 0.3 × 1013 cm−2. At higher current, the velocity slowly decreased with the electron velocity crossing below 107 cm/s at 1.8 A/mm. This behavior was found to be in good agreement with a previously proposed model based on optical phonon scattering at the source injection point. An analysis of the delay components is used to provide guidance for the factors influencing the device performance. [ABSTRACT FROM AUTHOR]

We present the cofabrication of planar Gunn diodes and high-electron mobility transistors (HEMTs) on an indium phosphide substrate for the first time. Electron beam lithography has been used extensively for the complete fabrication procedure and a 70-nm T-gate technology was incorporated for the enhancement of the small-signal characteristics of the HEMT. Diodes with anode-to-cathode separation ( \(L_{\rm ac}\) ) down to 1- and 120- \(\mu \) m width were shown to oscillate up to 204 GHz. The transistor presents a cutoff frequency ( \(f_{_{T}}\) ) of 220 GHz, with power gain up to 330 GHz ( \(f_{\max }\) ). The integration of the two devices creates the potential for the realization of high-power, high-frequency MMIC Gunn oscillators, circuits, and systems. [ABSTRACT FROM AUTHOR]

The carrier transport in advanced SiGe heterojunction bipolar transistor (HBT) process technologies exhibits bandgap-related transport effects that not only impact the transconductance and output conductance characteristics, but are also difficult to describe accurately by compact models. This paper addresses the modeling of bandgap-related effects in the collector current by formulating an improved version of a generalized integral charge-control relation (GICCR). As a result, the experimentally observed degradation of the transconductance at low and medium current injection, which is a strong function of the Ge grading, as well as the output conductance are described by simple bias- and temperature-dependent formulations of the GICCR weight factors. The derived formulations fit seamlessly into the compact model HICUM/L2. The extended model shows excellent agreement over a wide bias and temperature range with the experimental data of a large variety of SiGe HBTs from technologies of different manufacturers, including production and most advanced lab processes. [ABSTRACT FROM AUTHOR]