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Atomic layer deposition (ALD) has been studied extensively to employ oxide semiconductor thin film transistor (TFT) including both active layer and gate insulator (GI). Herein, we developed an ALD sandwich structure, which deposits both semiconductor and GI by ALD. In contrast to the previous results using sputter In-Ga-Zn-O (IGZO), ALD sandwich structure IGZO TFT exhibited severe deterioration in its electrical performance when the Al2O3 was adopted for both buffer layer and GI application. Through measurement of hydrogen permeability of ALD insulators and secondary ion mass spectroscopy of each sandwich structure after annealing, we found a hydrogen accumulation effect between Al2O3 and ALD IGZO interface layer, which caused deterioration of electrical performance. In contrast, TFTs with ALD SiO2, which has proper hydrogen diffusivity, chosen as the buffer and GI had favorable electric properties of 28.17 cm2/ $\text{V}\cdot \text{s}$ , 0.20 V/dec, 0.96, and 0.12 V for the mobility, ${V}_{\text {th}}$ , subthreshold swing (SS), and hysteresis. In this regard, an optimized GI structure via the ALD SiO2 and Al2O3 in situ process based on excellent interface formation with the semiconductor and hydrogen barrier performance, respectively, was developed. This functional GI structure consisting of SiO2 and Al2O3 exhibited excellent TFT characteristics (27.52 cm2/ $\text{V}\cdot \text{s}$ , 0.24 V/dec, and 1.07 V for the mobility, SS, and ${V}_{\text {th}}$ , respectively) with improved stability even after hydrogen annealing, which was used to examine the resistance to external hydrogen, showing a threshold voltage shift of −0.15 V and a SS shift of 0.01 V/dec. [ABSTRACT FROM AUTHOR]

A TCAD approach for the investigation of charge transport in thick amorphous silicon dioxide is presented for the first time. Thick oxides are investigated representing the best candidates for integrated galvanic insulators in future power applications. The large electric fields, such devices experience and the preexisting defects in the amorphous material, give rise to a leakage current, which leads to degradation and failure. Hence, it is crucial to have a complete understanding of the main physical mechanisms responsible for the charge transport in amorphous silicon oxide. For this reason, metal–insulator–metal structures have been experimentally characterized at different high-field stress conditions and a TCAD approach has been implemented in order to gain insight into the microscopic physical mechanisms responsible for the leakage current. In particular, the role of charge injection at contacts and charge build-up due to trapping–detrapping mechanisms in the bulk of the oxide layer has been investigated and modeled to the purpose of understanding the oxide behavior under dc- and ac-stress conditions. Numerical simulations have been compared against experiments to quantitatively validate the proposed approach. [ABSTRACT FROM AUTHOR]

A novel method of preparing reduced graphene oxide (rGO)–silicon (Si) junctions free from native silicon oxide layer at room temperature is reported. The method is based on a simultaneous reduction–dissolution reaction between graphene oxide (GO) and fresh Si atoms with the assistance of dilute hydrofluoric acid (HF). The rGO–Si junction is characterized by scanning electron microscopy, X-ray photoelectron spectroscopy, and atomic force microscopy. A reaction mechanism is proposed that Si is oxidized and dissolved by HF, which transfers the electronic holes to GO and facilitates the removal of its oxygen-containing groups. The use of HF provides a unique benefit to the contact formation that native oxide on Si is removed by HF instantaneously and only fresh Si surface is in contact with rGO. Therefore, the method provides a new strategy of preparing rGO-native oxide-free Si interface, which has been a fundamental challenge in the fabrication of graphene–Si junction. Electrical tests show that rGO–Si interface has a slightly higher barrier than Al–Si. [ABSTRACT FROM AUTHOR]

Electron emission (EE) from electron sources based on island metal films (IMFs) was mainly attributed to field emission or thermionic emission from IMFs. Here, we propose a new mechanism of EE from IMF-based sources, namely, EE from horizontal tunneling junctions formed in the substrate. The devices with and without IMFs fabricated on silicon oxide substrates are found to exhibit similar EE properties, while the island-metal-film-based devices fabricated on Si3N4/Si substrate show no EE. The comparative results indicate that EE originates from the underlying silicon oxide substrate that was ignored in previous mechanisms, but not from IMFs. EE from the devices is thought to be generated from horizontal tunneling junctions in electroformed silicon oxide substrate due to the rupture of conducting filaments. Even though metal island films are not the origin of EE, they can greatly decrease the forming voltage of the devices. The insights into the emission mechanism are helpful for optimizing the electron source performances. [ABSTRACT FROM AUTHOR]

Tilted ion implantation (TII) used in conjunction with preexisting masking features on the surface of a wafer is a relatively low-cost method for sublithographic patterning. Previous demonstrations of this method utilized a thin thermally grown layer of silicon oxide (SiO2) as the implanted layer, with amorphous-silicon masking features, to form patterns with feature sizes as small as 9 nm. In this article, this method is adapted to be compatible with back-end-of-line (BEOL) processing using silicon-containing antireflection coating (SiARC) as the implanted layer, with photoresist masking features formed using deep-ultraviolet (DUV) lithography. Negative-tone patterning of an ~15-nm-thick SiARC film is achieved by implanting Ar+ ions to selectively reduce its wet etch rate, allowing for the subsequent selective removal of the SiARC material from unimplanted regions. Patterned features down to 20 nm in lateral dimension are demonstrated. [ABSTRACT FROM AUTHOR]

The effects of trapped charges in gate dielectric and high- ${k}$ encapsulation layer on the performance of MoS2 transistor are investigated by using SiO2 with different thicknesses as the gate dielectric and HfO2 as the encapsulation layer of the MoS2 surface. Results indicate that the positive trapped charges in SiO2 can increase the electrons in MoS2 for screening the scattering of charged impurity (CI) in SiO2 and at the SiO2/MoS2 interface to increase the carrier mobility. However, the CI scattering becomes stronger for thicker gate dielectric with more trapped charges and can dominate the electron screening effect to reduce the mobility. On the other hand, with the HfO2 encapsulation, the OFF-currents of the devices greatly increase and their threshold voltages shift negatively due to more electrons induced by more positive charges trapped in HfO2. Moreover, the screening effect of these electrons on the CI scattering results in a mobility increase, which increases with the magnitude of the CI scattering. A 51% improvement in mobility is obtained for the sample suffering from the strongest CI scattering, fully demonstrating the effective screening role of high- ${k}$ dielectric on the CI scattering. [ABSTRACT FROM AUTHOR]

In this brief, nonvolatile memory (NVM) devices, based on the capacitor structure with the graphene nanosheets (GNSs) as the discrete charge storage media and atomic-layer-deposited (ALD) Al2O3 dielectric as the blocking oxide (BO) layer, have been demonstrated. The GNSs are formed by using the gold (Au) nanoparticles as the self-aligned mask and functionalized by using the NH3 plasma to enrich the charge trapping centers. In addition, the ALD Al2O3 layer is adopted as the BO layer of the GNS NVMs, resulting in a damage-free deposition on GNSs, compared to the conventional chemical-vapor-deposited SiO2 layer. The GNS NVM devices with a 15-nm-thick ALD Al2O3 BO layer can exhibit an excellent endurance of more than 105 cycles and superior data retention of lower than 30% charge loss for 10 years, suitable for future NVM applications. [ABSTRACT FROM AUTHOR]

In this paper, we investigated the influence of both source gas and deposition temperature in plasma-enhanced chemical vapor deposition (PE-CVD) for a SiO2 passivation layer on the electrical properties and reliability of a bottom-gate In–Ga–Zn–O thin-film transistor (IGZO TFT). Two gas chemistries consisting of SiH4–N2O–N2 and tetraethoxysilane (TEOS)–O2 were utilized as the source gases for the PE-CVD SiO2 deposition, and the deposition temperature (${T}_{D}$) was adjusted from 180 °C to 380 °C. The TFT properties were basically identical for both gas chemistries at ${T}_{D}$ of 180 °C. When ${T}_{D}$ increased to 300 °C or higher, the TFTs with the SiO2 passivation deposited by SiH4–N2O–N2 gas chemistry (SiH4-SiO2) drastically changed from the transistor to the conductor. In contrast, the TFT with TEOS-SiO2 passivation maintained its TFT characteristics even at ${T}_{D}$ of 380 °C, despite the degradation of subthreshold characteristics and a negative shift of turn-on voltage were observed due to an electron injection barrier lowering as ${T}_{D}$ increased to 310 °C or higher. We also revealed that a stacked SiO2 passivation that is deposited at a different ${T}_{D}$ is an effective technique to improve the performance and reliability of the IGZO TFT. [ABSTRACT FROM AUTHOR]

Resistive switching memory (RRAM) is among the most mature technologies for next generation storage class memory with low power, high density, and improved performance. The biggest challenge toward industrialization of RRAM is the large variability and noise issues, causing distribution broadening which affects retention even at room temperature. Noise and variability can be addressed by enlarging the resistance window between low-resistance state and high-resistance state, which requires a proper engineering of device materials and electrodes. This paper presents an RRAM device technology based on silicon oxide (SiOx), showing high resistance window thanks to the high bandgap in the silicon oxide. Endurance, retention, and variability show excellent performance, thus supporting SiOx as a strong active material for developing future generation RRAMs. [ABSTRACT FROM AUTHOR]

The cross-point architecture for memory arrays is widely considered as one of the most attractive solutions for storage and memory circuits thanks to simplicity, scalability, small cell size, and consequently high density and low cost. Cost-scalable vertical 3-D cross-point architectures, in particular, offer the opportunity to challenge Flash memory with comparable density and cost. To develop scalable cross-point arrays, however, select devices with sufficient ON–OFF ratio, current capability, and endurance must be available. This paper presents a select device technology based on volatile resistive switching with Cu and Ag top electrode and silicon oxide (SiOx) switching materials. The select device displays ultrahigh resistance window and good current capability exceeding 2 MAcm−2. Retention study shows a stochastic voltage-dependent ON–OFF transition time in the 10~\mu \texts –1 ms range, which needs to be further optimized for fast memory operation in storage class memory arrays. [ABSTRACT FROM PUBLISHER]

In this paper, implication (IMP) operations are demonstrated in a circuit with two SiOx-based memristors and a CMOS transistor. Specifically, a circuit with two one-diode and one-resistor (1D1R) memory elements and a transistor are designed to perform the IMP operations. A circuit consisting of a $4 \times 4$ crossbar 1D1R memristor array together with selection transistors is proposed and used to realize the functionality of a one-bit, full adder in 43 steps. Compared with CMOS logic circuits, the advantages and disadvantages of memristor-enabled logic circuits are discussed. This result suggests that the memristor-enabled logic circuit is most suitable for low-power and high-density applications, as well as a simple and robust approach to realize programmable memcomputing chips compatible with large-scale CMOS manufacturing technology. [ABSTRACT FROM PUBLISHER]

In this paper, we report on the anomalous behavior of threshold voltage ( V \sf th) with temperature in junctionless (JL) transistors. It is shown that both positive and negative values of temperature coefficient of threshold voltage (dV \sf th /dT) in nMOS Si and Ge JL devices can occur at higher drain biases. At lower temperatures, V \sf th reduces with a decrease in temperature due to the dominance of bipolar effects over thermal generation of carriers, whereas at higher temperatures, thermal generation results in essentially unipolar characteristics, and V \sf th reduces with increase in temperature. It is also shown that zero temperature coefficient condition shall be nonexistent under dominant bipolar conduction over unipolar operation. Results show new viewpoints to understand the two contrasting physical mechanisms leading to positive and negative dV \sf th /dT values in JL devices. [ABSTRACT FROM AUTHOR]

A physics-based 2-D analytical model for surface potential, electric field, drain current, subthreshold swing (SS) and threshold voltage of dual-material (DM) double-gate tunnel FETs (DG TFETs) with SiO2/HfO2 stacked gate-oxide structure has been developed in this paper. The parabolic-approximationtechnique, with suitable boundary conditions, has been used to solve Poisson’s equation in the channel region. Channel potential model is used to develop electric field expression. The drain current expression is extracted by analytically integrating the band-to-band tunneling generation rate over the channel thickness. Threshold voltage has been extracted by maximum transconductance method. The proposed model also demonstrates that the proper choice of work function for both the latterly contacting gate electrode (near the source and drain) materials which can give better results in terms of input-output characteristics, SS, and I \mathrm{\scriptscriptstyle ON}/I \mathrm{\scriptscriptstyle OFF} than the conventional TFET devices. Although the proposed model has been primarily developed for Si-channel-based DM DG TFET devices, however, the model has also been shown to be applicable for other materials like SiGe (indirect bandgap) and InAs channel-based TFET structures. The results of the proposed model have been validated against the TCAD simulation results obtained by using SILVACO ATLAS device simulation software. [ABSTRACT FROM AUTHOR]

The impact of the reverse-bias emitter-base stress and the mixed-mode stress on horizontal current bipolar transistor (HCBT) reliability characteristics is analyzed. Under the stress conditions, hot carriers are generated and injected toward silicon-oxide interfaces above and below HCBT’s emitter n+ polysilicon region where the traps responsible for the base current and beta ( $\beta $ ) degradations are formed. Different degradation rates of three HCBT structures measured under both stresses suggest various contributions of the top and bottom oxides to total damage. A larger contribution of the top interface under the reverse-bias emitter-base stress and of the bottom interface under the mixed-mode stress is determined. A lower doping concentration in the bottom part of the intrinsic transistor and a shorter emitter polysilicon predeposition oxide etching both reduce the generation of interface traps during stress tests. The time-dependent trap degradation simulations are run on the structures with the realistic doping profiles to explain the measured stress data on various HCBT structures. [ABSTRACT FROM AUTHOR]

The voltage and temperature dependence of post-breakdown (BD) conduction in SiO2 non-volatile memory bitcells is investigated. A model for charge transport in disordered systems is adapted to describe conduction through the BD path. The model uses a 2-D network of the quantum point contacts (QPCs) to simulate the oxide, and successfully reproduces the characteristics of experimental post-BD current in a large set of devices. Importantly, the temperature dependence in this model arises from the Fermi function rather than the structural changes in the oxide as suggested by previous studies. Once the QPC network model is fit to the experimental current–voltage ( $I$ – $V$ ) characteristics at one temperature, it is shown to correctly predict the $I$ – $V$ behavior at other temperatures without any additional parameters. Experimental $I$ – $V$ data from 100 devices that experience progressive BD are fit using the QPC network model, and for comparison, also using a single QPC model. We conclude that a QPC network gives a more realistic description of post-BD conduction than the single QPC model, as the network includes multiple path conduction and correctly describes the temperature dependence. [ABSTRACT FROM PUBLISHER]

Nanostructured silicon oxide impedance biosensors with ordered nanopores promise highly sensitive and selective label-free electrical detection of biomolecules through unique frequency-dependent sensitivity characteristics. Despite these promising experimental results, the fundamental mechanisms controlling the frequency-dependent phenomena and hence the design considerations have not been explored. In this paper, we consistently model the fluid and the solid regions of the sensors and discuss the design issues with respect to the pore dimensions for enhancing the sensitivity, selectivity, and repeatability toward detection of ultralow and moderate concentration of target biomolecules. The simulation results have been validated with experiments. The results indicate that the optimal design of nanoporous silicon oxide biosensors is different from the conventional idea of increasing the surface-to-volume ratio of such sensors. Instead, the design approach is nontrivial and the optimum pore dimensions are dependent on the target biomolecule charge, concentration, and distribution. It has been observed that a figure of merit is essential to design such sensors with improved commercial viability. [ABSTRACT FROM PUBLISHER]

In this paper, flexible silicon thin-film solar cells on polyimide are encapsulated by organic silicon and inorganic silicon oxide (SiOx) stacked layers. This encapsulation replaces conventional encapsulation, which involves ethylene-vinyl acetate (EVA). The effects of the number of stacked layers on encapsulation of silicon thin-film solar modules are investigated. Experimental results show that the six-pair stacked layer yields a water vapor transmission rate of as low as 10^-6 g/ \textm^\vphantom R^l2 day, satisfying the requirements of solar cell encapsulation. The measurements of internal stress confirm that a thin organic silicon layer greatly reduces the internal stresses over the whole device structure, preventing the cracking of SiOx and the consequent failure of the encapsulation. Solar modules that are encapsulated with a six-pair stacked layer not only exhibit a higher initial conversion efficiency than those encapsulated by EVA but also exhibit less performance degradation after being used outdoors for many hours. Bending test shows that after 5000 bendings, stacked layer encapsulation yields a device performance maintenance of 89.1%, while encapsulation in EVA maintains only 85.1% of device performance. These results suggest that silicon stacked layers have great potential for encapsulating flexible thin-film solar cells, and represent a favorable alternative to conventional EVA. [ABSTRACT FROM AUTHOR]

The effective work function (eWF) of Al-doped titanium carbide (TiAlC) metal electrodes prepared by atomic layer deposition shows a strong dependence on the underlying gate dielectrics. The eWF of TiAlC on HfO2 shows a low value of 4.2 eV independent of the deposition temperature and process conditions, whereas that on SiO2 shifted to a midgap value of 4.7 eV, and it was sensitive to the process conditions. The mechanism underlying this TiAlC work function dependence on different gate dielectrics is investigated in detail. [ABSTRACT FROM AUTHOR]

Multilevel resistive switching (RS) characteristics of silver programmable metallization cells (Ag-PMCs) with stacked SiOx/SiO2 solid electrolytes have been investigated. Combined with conventional high/low resistance states and additional two middle resistance states (MRS1/MRS2), a multilevel cell operation of stacked-solid-electrolyte Ag-PMCs is achieved and optimized by the film thickness. Furthermore, the RS mechanism at middle resistance states has been proposed to be locally discontinuous Ag conductive filament (Ag-CF) within the stacked solid electrolytes by examining the carrier transportation and two-frequency calibrated capacitance. The stacked silicon oxide layers can prevent the Ag-CF from regeneration during the multilevel retention test, contributing to the superior retention properties to more than 10^4 s at 125 °C. In addition, a sequentially multilevel cycling test of more than 10^3 times with a resistance ratio of two orders of magnitude between each resistance state is realized by the stacked-solid-electrolyte Ag-PMCs, suitable for future high-density nonvolatile memory applications. [ABSTRACT FROM AUTHOR]

Presents the table of contents for this issue of the publication. [ABSTRACT FROM AUTHOR]

A CMOS compatible AlN/SiO2/Si3N4/Si(100) surface acoustic wave (SAW) device has been fabricated and will be compared with standard AlN/SiO2-based devices. The presented filter demonstrates high potential for CMOS integrated high-frequency SAW devices. The filter insertion loss could be improved to −12.8 dB. The device exhibits high crosstalk suppression of −50 dB on a standard Si-substrate (10 $\Omega $ cm). X-ray diffraction, (scanning) transmission electron microscopy, and energy dispersive X-ray spectroscopy studies correlate the signal quality with $c$ -axis orientation of aluminum nitride films on interdigitated transducer finger electrodes. Finite-element method simulations are in good agreement with the electric measurements and show typical Rayleigh particle displacement. [ABSTRACT FROM AUTHOR]

We studied the environmental stability of amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) with single-layer (SiO2) and bilayer (SiO2/SiNx) passivation under high-humidity (80%) storage. During the 30 days of investigation, all single-layer passivated TFTs showed negative turn-ON voltage shifts ( \Delta V\mathrm{{\scriptstyle ON}} ), the size of which increased with storing time. The negative \Delta ~V\mathrm{{\scriptstyle ON}} is attributed to donor generation inside the active a-IGZO caused by the diffusion of ambient hydrogen/water molecules passing through the SiO2 passivation layer. The X-ray photoelectron spectroscopy depth profile for the SiO2 passivated structures confirms that the concentration of oxygen vacancies, which is initially larger at the a-IGZO/SiO2 interface, compared with the bulk a-IGZO, decreases after 30 days of storage under high humidity. This can be explained as the passivation of oxygen vacancies by diffused hydrogen. On the other hand, all bilayer passivated TFTs showed good air stability at room temperature and high humidity (80%). [ABSTRACT FROM AUTHOR]

The influence of etching-induced damage outside the depletion edge on the electrical characteristics of device is investigated using p-type metal-oxide–semiconductor structure with 2.5-nm SiO2 dielectrics. It is found that surface defects act as generation centers when minority carrier concentration is below equilibrium, leading to the increase of diffusion current injecting into depletion region. The saturation current in inversion region is an order larger for damage located at 5 $\mu $ m from the gate edge than that for damage free. On the contrary, the defects act as recombination centers when given light illumination. The saturation current in inversion region under illumination is reduced to one-fifth by etching-induced traps located at 5 $\mu $ m from the gate edge with respect to that without etching due to the reduction of diffusion current. A semiempirical current model based on the lateral diffusion current due to the modulation of minority carrier concentration outside the depletion edge is in great agreement with the experimental results by quantitative simulation. The model is applicable to devices involving etching process or surface issues, especially for those in the submicrometer regime. [ABSTRACT FROM AUTHOR]

In this paper, the laser power density is varied to increase the P2 laser spot size to investigate its effects on the performance of hydrogenated amorphous silicon-germanium (a-SiGe:H) thin-film solar modules. A larger P2 line spot size is expected to lower the series resistance of the modules, due to the increased contact area between the front and rear electrodes . However, increasing the laser power density faces several problems , which are: 1) damage of the SnO2 front electrode if the used power density exceeds the ablation threshold; 2) reduced quality of a-SiGe:H films; and 3) low spot size increasing rate at high power densities. The first can further lead to the presence of silicon oxide formation at the bottom of the P2 scribes. This paper demonstrates another method to obtain a larger spot size. A multiple P2 line scribing process has been performed to increase the spot size without deteriorating the film’s quality and the module performance. Finally, a 6-P2 linewidth of about 160 $\mu $ m leads to a balance between the gain in fill factor and the loss in photocurrent. The optimal module conversion efficiency of 8.82%, which is 8.7% higher than that using a single P2 line process, can be obtained. [ABSTRACT FROM AUTHOR]

An origin of shunt current, a ledge in forward current–voltage ( I – V ) characteristics, in 4H-SiC mesa p-n diodes was investigated by adopting various surface passivation processes. Experimental results indicated that the shunt current path is located along the mesa sidewall and the shunt current is enlarged with increasing NO-annealing period and temperature. Based on these results, we qualitatively explain that nitrogen-related positive charges near the SiC/SiO2 interface, which are formed by postoxidation nitridation, induce band bending and lowering of the diffusion potential along the mesa sidewall, resulting in occurrence of the shunt current. [ABSTRACT FROM PUBLISHER]

The buried oxide (BOX) layer in silicon on insulator (SOI) was replaced by a compound buried layer (CBL) containing layers of SiO2 , polycrystalline silicon (polysilicon), and SiO2 . The undoped polysilicon in the CBL acted as a dielectric with a higher thermal conductivity than SiO2 . CBL provides a reduced thermal resistance with the same equivalent oxide thickness as a standard SiO2 buried layer. Thermal resistance was further reduced by lateral heat flow through the polysilicon. Reduction in thermal resistance by up to 68% was observed, dependent on polysilicon thickness. CBL SOI substrates were designed and manufactured to achieve a 40% reduction in thermal resistance compared with an 1.0- \mum~SiO2 BOX. Power bipolar transistors with an active silicon layer thickness of 13.5 \mum manufactured on CBL SOI substrates showed a 5%–17% reduction in thermal resistance compared with the standard SOI. This reduction was dependent on transistor layout geometry. Between 65% and 90% of the heat flow from these power transistors is laterally through the thick active silicon layer. Analysis confirmed that CBL SOI provided a 40% reduction in the vertical path thermal resistance. Devices employing thinner active silicon layers will achieve the greater benefit from reduction in vertical path thermal resistance offered by CBL SOI. [ABSTRACT FROM AUTHOR]

Sputtered zinc oxide (ZnO) without intentional doping was thermally annealed and the dependence of its resistivity on different sample configurations and heat-treatment conditions was studied. The ZnO was either exposed to the ambience or sealed with an impermeable cover during the annealing. The resistivity resulting from the sealed configuration was found to be lower. The possible origins of the charge carriers responsible for the conductivity were investigated, with the most plausible one studied in greater detail using photoluminescence. The leakage current in the OFF-state of a field-effect thin-film transistor is largely controlled by the residual conductivity of the channel region of the transistor. For a ZnO transistor, this region is typically undoped and subjected to a series of thermal processes under a variety of coverage configurations during the course of the fabrication of the transistor. The implied correlation between the aggregate thermal treatment and the characteristics of a transistor in its OFF-state was investigated and demonstrated. [ABSTRACT FROM PUBLISHER]

In this paper, threshold voltage (VTH) stability of the ultrashallow body silicon-oxide-nitride-oxide-silicon gate power MOSFET (SG-MOSFET) under hot carrier injection conditions is characterized and discussed. Experimental results indicate that hot electron injection will increase the VTH from 1 to 2 V in the lifetime of the device. On the other hand, hot hole injection has no significant influence on the VTH stability of the device. The different effects caused by hot electron injection and hot hole injection are explained by using numerical analysis and experimental characterization, and results suggest that the VTH stability of the ultrashallow body SG-MOSFET will be improved if the short channel effect of the structure can be suppressed. [ABSTRACT FROM AUTHOR]

A Vt retention distribution tail in a multitime-program (MTP) silicon–oxide–nitride–oxide–silicon (SONOS) memory is investigated. We characterize a single-program-charge-loss-induced \Delta Vt in nor-type SONOS multilevel cells (MLCs). Our measurement shows the following: 1) A single-charge-loss-induced \Delta Vt exhibits an exponential distribution in magnitudes, which is attributed to a random-program-charge-induced current-path percolation effect, and 2) the standard deviation of the exponential distribution depends on the program-charge density and increases with a program Vt level in an MLC SONOS. In addition, we measure a Vt retention distribution in a 512-Mb MTP SONOS memory and observe a significant Vt retention tail. A numerical Vt retention distribution model including the percolation effect and a Poisson-distribution-based multiple-charge-loss model is developed. Our model agrees with the measured Vt retention distribution in a 512-Mb SONOS well. The observed Vt tail is realized mainly due to the percolation effect. [ABSTRACT FROM PUBLISHER]

We evaluated the effects of low-energy ultraviolet (UV) and visible light in organic thin-film-transistors, with an hexamethyldisilazane-treated \SiO2 gate dielectric. After visible-light irradiation, the devices showed temporary variation in the threshold voltage, drain current, and transconductance. When UV irradiation is performed, the devices exhibit significant and permanent degradation, with a transconductance drop up to -18%. [ABSTRACT FROM PUBLISHER]

This paper reports on the control of the direct-contact La-silicate/Si interface structure with the aim of achieving scaled equivalent oxide thickness (EOT) and small interface state density. The interface state density at the direct-contact La-silicate/Si interface is found to be reduced to \1.6 \times \10^11\ \cm^-2\eV^-1 by annealing at 800 ^\circ\C for 30 min in forming gas ambient, whereas excess silicate reaction concurrently induced a significant increase in EOT. By utilizing metal-inserted poly-Si (MIPS) stacks and their annealing at high temperature, the increase in EOT is drastically suppressed. At the same time, a superior interfacial property is obtained because the Si layer in the MIPS stacks prevents the excess oxygen diffusion from the atmosphere during the annealing process. As a result, the effective electron mobility of 155 \cm^2/\V\cdots at 1 MV/cm and an EOT of 0.62 nm are successfully achieved by utilizing direct-contact La-silicate/Si structure. This result is comparable with the recorded effective electron mobility achieved by utilizing Hf-based oxides/Si structure. This demonstrates the advantage of our proposed method to realize the scaled EOT with a superior interfacial property for state-of-the-art metal–oxide–semiconductor field-effect transistors. [ABSTRACT FROM PUBLISHER]

Despite theoretical predictions of significant performance improvement in Flash memory devices using tunnel-barrier-engineered (TBE) structures, there have been very few reports that demonstrate experimental verification. In this work, we have studied the role of factors such as high-k layer thickness and annealing recipe on the performance of \SiO2/\HfO2 gate stacks by electrical and physical characterization techniques. Results indicate that thick \HfO2 is not suitable for use in \SiO2/\HfO2 stacks for tunnel barrier engineering applications. The performance of \SiO2/\HfO2 stacks improves with decreasing thickness of the \HfO2 layer. Mild (10%) \O2/\N2 anneals do not significantly affect performance, although annealing above 600 ^\circ \C resulted in a slight decrease in the program current. Based on our observations, we propose a method to improve the program current in these structures and a simple hypothesis for the physical model for tunneling in \SiO2/\HfO2 stacks. [ABSTRACT FROM AUTHOR]

This paper presents vertical-Si-nanowire (SiNW) gate-all-around nonvolatile memory (NVM) devices of two different kinds: junction based and junctionless (JL). Si nanocrystals (SiNCs) and silicon nitride (SiN) are used as trap layers. The devices are fabricated using complementary-metal–oxide–semiconductor-compatible top-down process technology and compared on the bases of improved performance and reduced process complexity. The junction-based 50-nm vertical-SiNW memory device with a SiNC trap layer shows significant performance improvements on program/erase (P/E) speed and windows (3.5 V in 1-ms P/E at +\15/\!\!- \!\!\16\ \V) over a memory cell with a SiN trap layer (1.3 V in 1-ms P/E at +\15/\!\!-\!\!\16\ \V). On the other hand, the JL device with a SiN trap layer, realized on a highly scaled SiNW channel (down to 20 nm), is found to have comparable memory characteristics (3.2 V in 1-ms P/E at +\15/\!\!-\!\! \16\ \V) to a corresponding 20-nm SiNW junction-based cell (2.7 V in 1-ms P/E at +\15/\!\!-\!\!\16\ \V). Despite of that, the absence of junctions reduces process complexity and makes a vertical SiNW a suitable platform for multilevel stacked ultrahigh density memory applications. [ABSTRACT FROM PUBLISHER]

We have fabricated submicrometer ultralow-power thin-film transistors (TFTs) with stack gate dielectric structure formed by the nitric acid oxidation of Si (NAOS) method. A 1.8 nm NAOS \SiO2 layer effectively blocks the leakage current, and consequently, the thickness of a gate oxide layer deposited on the NAOS \SiO2 layer can be made as thin as 20 nm. Because of the thin gate oxide layer, submicrometer TFTs with gate length in the range of \0.6–\0.9 \ \mu\m can be fabricated. The operation voltage of the TFTs can be set as low as 1.5 V because of the low threshold voltages (i.e., -0.6 V for P-ch TFT and 0.6 V for N-ch TFT). The drain current versus source–drain voltage curves possess an ideal feature with sufficiently high saturation currents even at 1.5 V operation voltage. The drain current versus gate voltage curves show a sharp current increase, and the subthreshold swing value is \sim80 mV/dec for both P-ch and N-ch TFTs. The on/off ratio is \sim \!\!\10^9 for both P-ch and N-ch TFTs, and the channel mobility is \sim\!\!\100 \ \cm^2/\V\!\cdot\!\s for P-ch TFT and \sim\200 \ \cm^2/\V\!\cdot\!\s for N-ch TFT. [ABSTRACT FROM AUTHOR]

A fast response technique is developed to investigate the short-term postprogram and post-erase discharge in Flash memory devices. The procedure is based on fast VTH -evaluation methods developed for bias temperature instability and provides the transient characteristics after 20 ms under the program or erase conditions. The following different structures are investigated: 1) \SiO2/high-k stacks; 2) charge trap memories; 3) and floating gate memories. Dielectrics targeted for Flash memory applications are used as charge trap layers and interpoly dielectrics. In this paper, we show results on \Al2\O3, DyScO, GdScO, and hexagonal and perovskite LuAlO. The postprogram and post-erase curves hold useful information about the dielectric properties and are used as a fast screening technique for alternative materials. [ABSTRACT FROM PUBLISHER]

In this paper, we have proposed a simple and novel way to fabricate poly-Si nanowire (NW)-silicon-oxide-nitride-oxide-silicon (SONOS) devices with various gate configurations. Three types of devices having various gate configurations, such as side gated, \Omega -shaped gated \OmegaG, and gate-all-around (GAA), were successfully fabricated and characterized. The experimental results show that, owing to the superior gate controllability over NW channels, much improved transfer characteristics are achieved with the GAA devices, as compared with the other types of devices. Moreover, GAA devices also exhibit the best memory characteristics among all splits, including the fastest programming/erasing efficiency, largest memory window, and best endurance/retention characteristics, highlighting the potential of such scheme for future SONOS applications. [ABSTRACT FROM PUBLISHER]

A novel random telegraph signal (RTS) method is proposed to characterize the lateral distribution of injected charge in program and erase states in a nor-type silicon–oxide–nitride–oxide–silicon Flash memory. The concept of this method is to use RTS to extract an oxide trap position in the channel and then to use the trap and RTS as internal probe to detect a local channel potential change resulting from injected charge during program/erase. By using this method, the lateral width of the injected charge-induced channel potential barrier is shown to be around 20 nm in channel hot electron (CHE) program. Our method also confirms that Channel Initiated Secondary ELectron (CHISEL) program has a broader injected charge distribution than CHE program. A mismatch of CHE program electrons and band-to-band tunneling erase holes is observed. Program-state Vt retention loss models, charge vertical loss versus lateral migration, are reexamined by using this method. The polarity of a program-state charge distribution along the channel is explored within 10–20 program/erase cycles. Nitride charge vertical loss is verified by this method. [ABSTRACT FROM PUBLISHER]

\H3\PO4-incorporated nanocolumnar \SiO2-based proton conductors show an enhanced electric double layer (EDL) capacitance value of \sim\!\!\8 \ \mu \F/cm^2 at 20 Hz. The upper frequency limit of EDL formation is found to be higher than 10 kHz. Transparent indium–zinc–oxide (IZO) coplanar homojunction thin-film transistors gated by such proton conductors are fabricated by one metal shadow mask self-assembled method. The operating voltage is found to be as low as 0.6 V. The current on/off ratio, the subthreshold swing, and field-effect mobility are estimated to be \6 \times \10^5, 68 mV/dec, and 12 \cm^2/\V\cdot \s, respectively. Such transparent transistors hold promise for low-cost and portable electrochromic devices and invisible biochemical sensors. [ABSTRACT FROM PUBLISHER]

From the measured data, the impact of the rapid thermal process (RTP) and laser spike anneal (LSA) sequence on negative bias temperature instability (NBTI) and current gain was investigated on 40-nm complementary metal–oxide semiconductor technology. For the conventional sequence RTP/LSA, a significant threshold voltage VT shift is observed due to the NBTI. The thermal gradient in the LSA step induces a thermomechanical stress inducing oxide fixed charges and an increase in Si dangling bonds at the SiON/Si interface, thus increasing the VT shift. By moving the LSA step to before the RTP anneal and coimplanting a carbon atom in the source/drain extension implant processing, the obvious VT shift could be suppressed to the same as the RTP-only anneal. Best of all, the sequence change does not impact the gain of the original combination anneal over the RTP-only anneal in the on current of devices. [ABSTRACT FROM PUBLISHER]

Transistor mismatch data and analysis from poly/SiON and high-k/metal-gate (HKMG) bulk CMOS technologies are presented. It is found that the traditional mismatch figure of merit from the Pelgrom plot (AVT) continuously scales down as technology advances. Furthermore, the AVT values for both nFET and pFET in the HKMG technology are significantly reduced from poly/SiON technologies. By normalizing the mismatch data against electrical oxide thickness (TINV), threshold voltage (VTH), and effective work function, a direct comparison of the mismatch data from various technologies is made. The differences in nFET and pFET mismatch behaviors in both poly/SiON and HKMG technologies are discussed in detail. Correlation between transistor VTH mismatch and flicker noise variation is observed in both poly/SiON and HKMG technologies. Finally, it is quantitatively demonstrated that effective work function variation does not generate significant VTH variability in the present HKMG technology. [ABSTRACT FROM AUTHOR]

A simple self-assembling approach with only one nickel shadow mask is developed for flexible transparent thin-film transistors (TFTs) with patterned channel fabrication. An ultralow operation voltage of 1.5 V is realized due to the large specific gate capacitance (1.5 \mu\F/cm^2) of the microporous \SiO2-based solid-electrolyte dielectric. Flexible transparent indium–tin-oxide TFTs exhibit a good performance with a low subthreshold swing of < 70 mV/dec and a large on/off ratio of \sim\!\!\10^7, respectively. Such low-voltage flexible transparent TFTs with a simple self-assembling process are promising for portable flexible transparent electronics applications. [ABSTRACT FROM AUTHOR]

For the first time, a high-performance (\tauPGM =\break \200 ns\!/\!\tauERS\! = \5 ms) cell with superior reliability characteristics is demonstrated in a nor-type architecture, using dynamic-threshold source-side injection (DTSSI) in a wrapped select-gate silicon–oxide–nitride–oxide–silicon memory device, with multilevel and 2-bit/cell operation. Using DTSSI enables easy extraction of the multilevel states with a tight VTH distribution, a nearly negligible second-bit effect, superior endurance characteristics, and good data retention. [ABSTRACT FROM PUBLISHER]

We propose a novel 4-bit self-aligned SONOS-type nonvolatile memory (NVM) cell with a T-gate and I-shaped FinFET structure for practical implementation with high storage density and better reliability. In order to obtain enhanced reliability characteristics, a modified Fowler--Nordheim tunneling mechanism is employed for programming along the channel length direction, while a band-to-band hot hole injection is used for erasing along the channel width direction. With separated paths for program and erase, improved device performance is obtained with sensing margin. In order to improve the immunity to second-bit effects, the gate-induced drain leakage current method, which is a charge detection method and highly sensitive to the locally stored charges, is employed for the reading of the stored data. In terms of the scalability, we confirmed by 2-D technology computer-aided design simulation that the proposed NVM cell with channel length L = 50 nm operates with enough sensing margin and high-density (~5 F²/bit) NVM by the crossed cell array architecture. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the specific impact of an additional silicon oxide layer (sealing oxide) on top of the charge-trap nitride on the electrical performance of small-dimension and large TANOS charge-trapping (CT) memory cells. We observe a significant improvement in charge retention on both our target 48-nm NAND TANOS cells and on large 5 µm long and wide memory cells. However, erase performance is partially degraded by this additional silicon dioxide top-dielectric layer. The presented intrinsic CT stack retention for 3.5-nm sealing oxide, which is visible on large cell structures, clearly shows the potential for multilevel cell operation. We further identified trapping in the Al2O3 states of the blocking dielectric to improve the program and erase performance of conventional TANOS memory cells. However, detrapping from these trap states was found to be the root cause of insufficient retention. [ABSTRACT FROM AUTHOR]

A combination of density functional theory and nonequilibrium Green's function formalism has been applied to the atomic scale calculation of the leakage current through SiO2 and SiOxNy dielectrics of MOSFETs. Samples with different dielectric thicknesses and nitrogen concentrations have been taken into account in order to study the dependence of the leakage current on these two parameters. It has been shown that the incorporation of nitrogen atoms into SiO2 increases the density of gap states, which leads to barrier lowering for both electrons and holes. The calculated leakage currents through different SiO2 polymorphs (e.g., β-cristobalite, α-quartz, and β-quartz) show thickness dependences, which are in very good agreement with measured values for amorphous SiO2. The dependence of the leakage current on the concentration of nitrogen atom in oxynitride gate dielectrics has also been calculated and shown to be in good agreement with the values extracted from measured data. [ABSTRACT FROM AUTHOR]

Unified random access memory (URAM) with a separated double-gate is demonstrated on a fully depleted polysilicon (poly-Si) thin-film-transistor (TFT) template. Integration of a front-gate dielectric of tunneling oxide/nitride/control oxide (O/N/O) and a floating poly-Si channel provides the two versatile functions of nonvolatile silicon oxide--nitride oxide--semiconductor Flash memory and high-speed capacitorless single-transistor 1T-DRAM in a single transistor. In this design, the memory mode of URAM is selected according to user specifications. As the back-channel is assigned for capacitorless 1T-DRAM while the front-channel is devoted for Flash memory, spatial separation minimizes undesired soft programming in the front O/N/O layer and allows for capacitorless 1T-DRAM operation irrespective of the data state of the nonvolatile memory. This feature presents interference-free operation between the two modes. In addition, the virtue of the TFT process allows the potential for stackable memory for ultra-high-density era. [ABSTRACT FROM AUTHOR]