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The Reaction Diffusion Drift (RDD) model is incorporated in the Sentaurus Technology CAD (TCAD) framework and coupled with carrier and lattice heating to calculate the generation of traps during channel hot carrier stress. The parametric shift due to these generated defects, localized near the drain junction of the device, is calculated under different combinations of gate and drain bias stress. The developed TCAD framework is validated against measured data for devices having varying gate length, oxide thickness, and junction structure. The ability of the framework to reproduce measured time kinetics, gate and drain bias, and temperature dependence is demonstrated. The absence of recovery after hot carrier stress is explained using the stochastic implementation of the same model. A 1-D standalone version of the same model, having identical time kinetics as TCAD, together with the Bias Temperature Instability (BTI) analysis tool discussed in Part I, is used to isolate the BTI and pure Hot Carrier Degradation (HCD) contribution during HCD stress. An equivalent compact model is used for cycle-by-cycle simulation of circuit aging due to HCD in different Ring Oscillator (RO) stages, by using the framework discussed in Part I. The error associated with blanket assignment of AC-to-DC ratio is demonstrated.