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A trench split gate metal-oxide-semiconductor field-effect transistor (MOSFET) inductive switching is analyzed by adopting six-terminal method. Owing to the buried source terminal in the trench oxide, conventional three-terminal (gate, source, and drain) analysis has a limitation for investigating the detailed time-dependent current flow in the drift region, channel, as well as each terminal. However, a mixed-mode simulation tools enable us to look into the complicated current flow mechanisms in the device by dividing the gate terminal into the gate-to-source and the gate-to-drain terminals and the source terminal into the ${n} +$ , the ${p} +$ , and the shielded source terminals. The six-terminal method enables us to understand the fundamental turn-on and turn-off switching mechanisms that we have not found out so far from the measurement. [ABSTRACT FROM AUTHOR]

In this work, we analyze the impact of random dopant fluctuations (RDFs) on the mismatch behavior of the negative capacitance field-effect transistor (NCFET). We observe that the drain current mismatch decreases in the NCFET compared to conventional MOSFET, and it further decreases with an increase in the thickness of the ferroelectric layer (${t}_{\text {fe}}$). Metal–ferroelectric–metal–insulator–semiconductor (MFMIS)-type NCFET shows 24% and 22% improvement in mismatch power in comparison to baseline FET at $\vert {V}_{\text {GS}}\vert = {0.2}$ and 1 V, respectively. We show that the mismatch in NCFET is directly proportional to channel doping concentration, similar to baseline MOSFET. For the first time, we demonstrate that mismatch power varies nonmonotonically with the variation in the Landau coefficient $\alpha $ , and the other Landau coefficient $\beta $ has an impact on mismatch at higher ${t}_{\text {fe}}$ only. We also present a compact model, under the industry standard Berkeley Short-channel IGFET Model for Bulk MOSFET (BSIM-BULK) MOS model’s framework, which can accurately capture drain current mismatch from subthreshold to strong inversion region for NCFET. The model is extensively validated with the experimentally calibrated technology computer-aided design (TCAD) simulations across different biases and temperatures. [ABSTRACT FROM AUTHOR]

Shallow trench isolation drain extended MOS (STI-DeMOS) devices, known for their superior gate oxide reliability under high drain voltages, are widely used for the integration of CMOS-compatible high-voltage devices. However, they offer moderate high-frequency performance that limits the use of these devices even in mid-band 5G applications. A novel island drain and a double-gate drain-extended MOS (IDDG DeMOS) device with improved high-frequency performance is proposed in this work. The proposed device has a core MOSFET and an STI-DeMOS with a self-aligned pocket well, both feature a shorter channel length than a typical STI-DeMOS device. The shorter gate length enhances the proposed device’s RF performance without degrading the breakdown voltage. We have performed simulations using a well-calibrated deck in the Sentaurus TCAD environment. We have shown an increase in the transit frequency from 25 GHz in STI-DeNMOS to 53 GHz in the proposed IDDG DeNMOS device, and from 11 to 31 GHz for a p-type device at a 65-nm technology node. This work also presents the well edge variation immunity of the proposed device. All these features are achieved in the mainstream SoC-compatible CMOS process flow without any additional fabrication mask or process complexity. [ABSTRACT FROM AUTHOR]

A novel comb-like-channel field-effect transistor (CombFET), which is the combination of the fin field-effect transistor (FinFET) and nanosheet FET (NshFET) geometries in the channel region, is proposed and evaluated numerically for the first time. Our simulations show that: 1) with the same footprint, CombFET ON-current is 43% higher than FinFET and 53% higher than gate-all-around FET (GAAFET) due to its larger effective channel width and relieved channel quantum confinement and 2) CombFETs have great advantages in performance optimization through surface orientation over FinFETs and NshFETs. Thanks to the unique structural design, CombFET can also be used to improve or eliminate the bending or adhesion effects between nanosheets/comb teeth. [ABSTRACT FROM AUTHOR]

An accurate density of states (DOS) is essential for understanding charge carrier transport properties and then better developing the electronic and optoelectronic devices. Currently, Gaussian and exponential forms are the two most general DOS, which can be unified in the tail state of the state. However, Gaussian DOS at high concentrations is not applicable, as well as exponential DOS at low concentrations. To avoid the disadvantage of Gaussian and exponential form, based on the Poisson flow, a unified distribution form of the DOS have been developed to discuss the charge carrier transport. The proposed DOS is more consistent with the actual situation and exhibits better rationality under the whole range of carrier density. Otherwise, we for the first time introduced the entropy to analyze the disorder parameters. Based on the proposed DOS, the concentration and temperature dependence of mobility has been discussed in detail. [ABSTRACT FROM AUTHOR]

SiC MOSFETs have received great attention due to their excellent electrothermal properties. Accurate junction temperature information of SiC MOSFETs ensures safe operation and helps effective thermal management. However, the existing thermal models have limits to correctly predict the thermal behaviors, whose parameter extraction processes are normally complicated. Most of the thermal models generally omit the temperature effects, which greatly impairs their usefulness and effectiveness. Here, a temperature-dependent physical resistor–capacitor (RC) network model is proposed, which can accurately characterize the thermal behavior of SiC MOSFETs particularly under high-temperature conditions. Meanwhile, the boundary conditions are fully investigated and modeled, which guarantees the adaptation of the proposed model for different real-field applications. The proposed method can remarkably simplify the process of parameter extraction since only the steady-state temperature distribution information is required with the assistance of finite-element method (FEM). Finally, the effectiveness and the robustness of the proposed model are validated by FEM simulation and experiments. [ABSTRACT FROM AUTHOR]

In this article, an analytical thermal conductivity model considering the degradation caused by the different phonon scattering mechanisms is presented for studying the self-heating effects (SHEs) in ultrathin body and buried oxide (UTBB) silicon-on-insulator (SOI) MOSFETs. By allowing for phonon-boundary and phonon–electron scattering, as well as tuning the surface roughness, the model enables accurate predictions for silicon films of different thicknesses over a wide temperature range. In order to apply the temperature-dependent self-built thermal conductivity model to the technology computer-aided design (TCAD) electrothermal simulation, a piecewise fitting, and equivalent strategy is developed by using the zero points (ZPs) and extreme points (EPs) of the first- and second-order discrete differentials of the model. The results show that the modified model is closer to the experimental data from literature studies than the default TCAD model in predicting the thermal conductivity distribution of the SOI-structure. Furthermore, the TCAD simulation results with our modified model show the same trend as that with its default model in predicting the performance degradation of UTBB SOI devices due to SHEs, such as the degradation of carrier mobility in the channel and the increase of subthreshold swing (SS). [ABSTRACT FROM AUTHOR]

A new deep learning (DL)-based parameter extraction method is presented in this brief; 50k training cases are generated by Monte Carlo simulations of these preselected parameters in Berkeley short-channel IGFET model (BSIM)-common multigate (CMG). DL models are trained using backward propagation with ${C} _{\text {gg}} - {V} _{g}$ and ${I} _{d} - {V} _{g}$ as the input and selected BSIM-CMG parameters as the output. A TCAD simulated FinFET device, calibrated to Intel 10-nm node, is used to test the DL models. The DL-based parameters extraction results show an excellent fit to capacitance and drain current data, with 0.16% rms error in ${C} _{\text {gg}} - {V} _{g}$ and 6.1% rms error in ${I} _{d} - {V} _{g}$ (0.69% rms error in above-threshold-voltage ${I} _{d} - {V} _{g}$), respectively. In addition, devices with a 10% variation in gate length and oxide thickness are successfully modeled with the trained DL model. The results show tremendous promise in using the DL-based models for parameter extraction. [ABSTRACT FROM AUTHOR]

In this work, a scalable robust substrate current model for laterally diffused MOS (LDMOS) transistors is presented. The model is created in two stages. First, a model for intrinsic drain voltage, which accurately captures the modulation of intrinsic drain voltage with applied gate and drain voltages, is developed. This model is then used to derive an expression for the substrate current. The accuracy of the substrate current model is verified by comparing it with the data measured from LDMOS transistors with different device dimensions. The model accurately captures the modulation of substrate current with bias voltages and shows excellent scalability. Different LDMOS designs are also suggested to reduce the substrate current at the same OFF-state breakdown voltage. [ABSTRACT FROM AUTHOR]

Correlated multiple sampling (CMS) is a popular oversampling technique that is widely integrated into recent low-noise CMOS image sensors (CISs). In its common implementation equal weights on both reset and signal samples are applied to compute a low-noise signal sample. In this article, we analyze the effectiveness of four oversampled techniques on CIS read noise performance. We compare CMS, noise optimized correlated multiple sampling (NOCMS), skipper multiple sampling (SMS), and noise optimized skipper multiple sampling (NOSMS). We verify our model on a sensor offering CMS functionality. We derive noise parameters based on regular correlated double sampling (CDS) measurements, and then compute CMS noise estimates using our model. We obtain good agreement between model and measurements. We then use model parameters of two sensors to compare the four oversampling techniques. We point out that floating diffusion (FD) leakage current becomes a dominant noise factor in CMS, which NOCMS can greatly reduce. Finally, we conclude that SMS and NOSMS have more potential to further reduce read noise than CMS or NOCMS. [ABSTRACT FROM AUTHOR]

A unified model for multigate negative capacitance transistors with self-heating effects (SHEs) is developed. With a metal–ferroelectric–insulator–semiconductor (MFIS) structure, thermal effects result in different temperature rises in the channel and ferroelectric layer. A gate control equation for the double-gate and gate-all-around MFIS structures is developed, on top of which both the current–voltage and charge–voltage characteristics are covered. The formulations describe dependences of ferroelectric layer thickness, with backward compatibility for MOSFETs. A unified thermal network is then proposed for SHE, capturing the essential physics of couplings between ferroelectric temperature and conduction current. The model has been verified with TCAD simulations and implemented for circuit simulations. [ABSTRACT FROM AUTHOR]

Heterostructure engineering in III-V vertical nanowire (VNW) MOSFETs enables tuning of transconductance and breakdown voltage. In this work, an InxGa $_{{1}-{x}}$ As channel with a Ga-composition grading (${x} \,\,=$ 1–0.4) in the channel and drain region, combined with field plate engineering, enables breakdown voltage above 2.5 V, while maintaining transconductance of about 1 mS/ $\mu \text{m}$ , in VNW MOSFETs. The field plate consists of a vertically integrated SiO2 layer and a gate contact, which screens the electric field in the drain region, extending the device operating voltage. By scaling the field plate, a transconductance of 2 mS/ $\mu \text{m}$ , alongside the breakdown voltage of 1.5 V, is obtained, demonstrating the benefit of field engineering in the drain. The scalability of the field plate and the gate is measured, showing an ON-resistance increase by 23 $\Omega \cdot \mu \text{m}$ , and transconductance decrease by 5 $\mu \text{S}/\mu \text{m}$ , per nm field plate length. This behavior is captured in a new and modified virtual source model, where device transmission and drain resistance are altered to capture the field plate scaling effect. The modeling is applied to nanowire (NW) devices with field plate lengths ranging from 5 to 115 nm, capturing accurately essential device performance parameters. Finally, a modified band-to-band (BTB) tunneling approach is used to accurately describe the device behavior above 1.5 V. [ABSTRACT FROM AUTHOR]

Due to the potential for technological application, there has been an explosion of interest in heavily polycrystalline ferroelectric nanofilms, such as those of doped hafnium oxide. However, the heavily polycrystalline nature of these materials invalidates conventional modeling approaches as the dynamics have been found to be: 1) nucleation-limited; 2) involve grains of ferroelectric material interspersed among grains of alternative, nonferroelectric material; and 3) the direct interaction between these grains is observed to be minimal. In this article, we consider seven separate compact or “0-D” models of such polycrystalline films. Four of these models are based on a Landau paradigm and two are based on a Monte Carlo (MC) paradigm. The seventh is the traditional Preisach model. Although all of these models have been used in the literature to model novel polycrystalline ferroelectric nanofilms, here we compare and contrast the accuracy and physical appropriateness of each model by comparing both their static and dynamic properties against experimental data. We then find that although all models except single-grain models are capable of reproducing the static properties, only the MC models replicate the long-time dynamical properties. Thus, it is demonstrated that not all models are equally valid for the accurate modeling of such films. [ABSTRACT FROM AUTHOR]

Si-based cold source field-effect transistor (CSFET) combines the benefits of sub-60-mV/dec steep-slope switching, high ${I}_{ \mathrm{\scriptscriptstyle ON}}$ current, and compatibility with current Si CMOS process technology. Therefore, it is a promising candidate for future energy-efficient logic technology. For the first time, we present device and circuit benchmark of Si-based gate-all-around (GAA) CSFET versus conventional GAA MOSFET. The device’s characteristics are first generated using a calibrated multiscale TCAD framework. Then a novel SPICE device compact model based on neural network is created to capture the unique CSFET ${I}-{V}$ and ${C}-{V}$ data with high precision. This SPICE model further enables the circuit benchmark simulations. Through this approach, it is identified that compared with GAA MOSFET, Si-based GAA CSFET shows up to 67% performance/power gain for a supply voltage (${V}_{\text {dd}}$) below 0.43 V in an ideal gate-loaded ring oscillator circuit. It is 70% more energy-efficient in the capacitive-loaded fan-out of 4 (FO4) inverter circuit. Finally, the comparisons of GAA CSFETs with different nanosheet widths are accomplished for design technology cooptimization (DTCO) purpose. [ABSTRACT FROM AUTHOR]

A universal equation for the charge-voltage characteristics in the multigate metal oxide semiconductor (MOS) structure with an arbitrary cross section is presented. A generalized coordinate is proposed and the Poisson equation is integrated with a weighting factor related with the generalized coordinate and the electric field. A compact charge model is derived and analytic and numerical examples for various MOS structures are shown. [ABSTRACT FROM AUTHOR]

CMOS single-photon avalanche diode (SPAD) array is a high-timing-resolution photon-counting image sensor. Pixel size shrinkage for high image resolution is highly desirable but hindered by the lowered photon-detection-probability (PDP) as the edge area becomes significant. We propose and demonstrate a parameter-free method for simulating PDP with the edge effect. Considering the doping profile, electric field, photon generation, and trigger probability distributions in two dimensions, the PDP reduction at the device edge is analyzed in a quantitative way. Besides, a novel guard-ring design for enhancing PDP of small SPAD has been proposed and simulated by our method. A threefold enhancement was obtained with the newly designed guard-ring structure compared with the original one. Our work is useful for developing small-pitch SPAD array for high-resolution imaging applications. [ABSTRACT FROM AUTHOR]

Recently, p-type tin monoxide (SnO) thin-film transistors (TFTs) have gained interest for all-oxide complementary metal–oxide semiconductor (CMOS) circuits for flexible electronics and back-end-of-line integration with Si. However, most SnO TFTs demonstrated so far exhibit a low on– off-current ratio and limited field effect mobility. To understand and improve SnO TFT performance, it is necessary to quantitatively characterize the subbandgap defects in SnO and at its dielectric interface. In this work, we establish numerical models which provide this understanding. By concurrent fitting of simulated ${I}_{\text{D}}$ – ${V}_{\text{GS}}$ and effective mobility versus ${V}_{\text{GS}}$ to experimentally measured data, we can accurately extract SnO defect state profiles. Using the extracted simulation models, we then identify ways to improve SnO TFT performance. Specifically, a reduction in the density of shallow, bulk Gaussian acceptor states, is necessary to reduce the off-current, while reducing the contact resistance and interface donor-like tail state density can improve the SnO field effect mobility. [ABSTRACT FROM AUTHOR]

In this article, a physics-based analytical current model for armchair graphene nanoribbon field-effect transistors (A-GNRFETs) is developed, which is valid from ballistic to quasi-ballistic transport regimes. The roles of line-edge roughness (LER) for different roughness parameters and Fermi level of GNRs are numerically investigated. Furthermore, the effect of LER-related tunneling current has a strong impact on the drain–source current for the OFF state, and it is considered in this model. The good agreement between our proposed current model and the nonequilibrium Green function (NEGF) simulations proves its validity. The results indicate that depending on the geometrical and roughness parameters, the transport properties can be ballistic or quasi-ballistic. [ABSTRACT FROM AUTHOR]

The understanding of self-heating effects and heat dissipation in semiconductor devices is a necessary element for the accurate modeling and prediction of reliability indicators. Unfortunately, the small dimensions, the complex device structures, and the presence of thin-oxidized interfacial layers make it impractical to determine these quantities experimentally. In this work, we calculate electrical conductances (${\sigma }$), electronic thermal conductances (${k}$), and their respective Lorenz numbers [ $\text {L}={k}/{(}\sigma {T}\,{)}$ ], for materials and relevant interfaces at the BEOL and MOL levels in advanced CMOS technologies. We progress from bulk to pure metal interfaces to realistically oxidized interfaces, and find the model works well, enabling a physical understanding of the impacts of oxidation, unavoidable in high-volume manufacturing. We find that Wiedemann–Franz (W–F) law applies very well for these metallic interfaces with Lorenz numbers being close to the bulk counterpart. We also find that interface oxidation exponentially increases the interface resistances. This can readily enable thermal characterization of these interfaces through electrical measurements, allowing accurate self-heating modeling for FinFET and beyond technologies. [ABSTRACT FROM AUTHOR]

Ferroelectric field-effect transistors (FEFETs) are an important candidate for emerging nonvolatile memory applications but suffer from a lack of physical understanding of the device operation. Previous FEFET models utilized the Preisach model of ferroelectrics and do not accurately capture the physics of the FEFET that the majority of the polarization charge is screened by trapped charge at the interfaces. We propose an empirical model for FEFETs, which also considers screening of ferroelectric polarization. The screening charge is modeled as a dissipative (leakage) current across the baseline MOS gate-stack. The proposed model is calibrated using the experimental data of p-type ZrO2 FEFETs and unravels the weak electrostatic coupling between the ferroelectric polarization and semiconductor channel charge. In addition, the model captures the memory window discrepancy between the charge–voltage characteristics and current–voltage characteristics observed in the experimental data, provides new insight into the ferroelectric device, and is well-suited for use as a compact model implementation of FEFETs. [ABSTRACT FROM AUTHOR]

We propose an n-ZnO/p-SnOx heterojunction solar cell as a novel pathway to realize all-oxide photovoltaics that offer attractive features such as stability, cost-effectiveness, and nontoxicity. TCAD device simulator was used to investigate the performance of n-ZnO/p-SnOx thin-film solar cell using inputs on material parameters of SnOx obtained experimentally. In this study, we considered the effects of SnOx parameters, namely, bandgap and electron affinity on the performance of solar cell. Electrical transport models applied in modeling include the effects of interfacial recombination, tunneling, band discontinuity, and minority carrier lifetime. Our simulation results show that a maximum power conversion efficiency of ~15.5% can be obtained in a window of an optimum combination of bandgap and electron affinity of SnOx layer. Further enhancement in efficiency is achievable by improving the minority carrier lifetime. [ABSTRACT FROM AUTHOR]

In the design of memristive chips, memristor models are needed to evaluate the correctness of circuit design and simulation. Although numerous memristor models exist, they are usually too complicated to exhibit satisfactory simulation speed in large-scale arrays, or too concise to accurately reflect device characteristics. In this article, we propose a PieceWise linear (PWL) memristor model with well-balanced simulation speed and accuracy. The model has continuous state equation and contains only elementary operations to guarantee the simulation efficiency. The model parameters are derived with the minimum mean square error (MMSE) fitting method from the measured data. Simulation results illustrate that, with similar fitting accuracy, our model can reduces simulation time by 30% and memory usage by 11% than state-of-the-art models in a pure network with over $2\times 10^{4}$ memristors. The effectiveness of this model is also validated in a $32\times 64~1$ T1R array with weight update and signal processing operations. [ABSTRACT FROM AUTHOR]

In this article, the planar $\beta $ -Ga2O3 junctionless transistors with/without unintentional doping (UID) buffer layer are numerically investigated. It was found that the double-layer Ga2O3 MOSFETs (epilayer/buffer layer) show a trade-off between threshold voltage (${V}_{\text {th}}$) and device reliability (resulting from anomalous Fe out-diffusion), as a function of the thickness (${T}_{\text {buf}}$) and carrier concentrations (${N}_{\text {buf}}$) of $\beta $ -Ga2O3 buffer layer. The simulation results show that an adequate buffer layer (200 nm $ < {T}_{\text {buf}} < {500}$ nm, ${N}_{\text {buf}} < {5}\times {10}^{{14}}$ cm−3) is beneficial to the pinch-off characteristic of $\beta $ -Ga2O3 planar MOSFETs. A novel triple-layer MOSFET (introducing a low-doped $\beta $ -Ga2O3 surface layer above the epilayer) is subsequently proposed and demonstrated to be an easy pathway to modulate ${V}_{\text {th}}$ by adjusting the thickness and doping concentration of surface layer. In addition, the effect of the lateral extension N+ region is also discussed. As a result, the triple-layer $\beta $ -Ga2O3 MOSFET with an optimized dimension can achieve positive enhancement-mode and better device performance: breakdown voltage (${V}_{\text {br}}$) and power figures of merit (P-FOM) are improved by 173.71% and 65.37%, respectively, while specific ON-resistance is increased by 391.35%. [ABSTRACT FROM AUTHOR]

An analytical drain current model is developed for a short-channel, dual-gate, monolayer 2-D transition metal dichalcogenide (TMD), lateral tunnel field-effect transistor (TFET) by considering 2-D ${p}^{+}-{n}$ and ${n}-{n}^{+}$ junction at source–channel and channel–drain junction, respectively. This work includes the effect of both front- and back-gate dielectric fringing field effects and 2-D source and drain depletion charges. A unified piecewise surface potential model is developed by capturing the fringing field effects in the channel and 2-D junction behavior at the source–channel and channel–drain junction by ensuring continuity of electric field at the junction regions. A tangent-line approximation method is employed for accurate numerical evaluation of the tunneling current. The proposed model is validated with simulation results obtained using nonequilibrium Green’s function (NEGF)-based simulator for different 2-D layered materials and a close agreement is observed. The veracity of the proposed model is tested with data in reported studies for different bias conditions and excellent matching is observed. The applicability of the model is demonstrated for any 2-D layered material-based TFET from ultrashort channel to a channel length of 50 nm. The proposed model will be extremely useful for further exploration of 2-D TMD material TFET-based very large-scale integration (VLSI) circuits. [ABSTRACT FROM AUTHOR]

The impact of process-induced inclination angle ($\theta $) of nonvertical sidewalls of the fabricated quadruple gate (QG) metal–oxide–semiconductor field-effect transistor (MOSFET) on subthreshold characteristics has been analytically modeled and analyzed using the equivalent width, equivalent oxide, and coupling between the two equivalent double gate (DG) MOSFETs. A quasi-3-D scaling length model has been formulated accounting $\theta $ and corner gates, which was subsequently applied to derive the channel center potential, threshold voltage, subthreshold current, subthreshold swing (SS), and noise margin (NM) for subthreshold logic applications of trapezoidal (Tz) gate-all-around (GAA) MOSFETs. The newly formulated models were successfully verified using TCAD calibrated to the experimental results of our fabricated QG-MOSFETs. We found that for channel length, ${L}_{g}$ = 50 nm, Fin height, ${H}_{Fin}$ = 20 nm, and Fin top width, ${W}_{top}$ = 10 nm, the potential barrier of TzGAA MOSFET falls by 4.7% at $\theta =30^\circ $ compared to rectangular cross section, thereby, deteriorating the short-channel immunity of the device. The SS roll-up, threshold voltage roll-off, drain induced barrier lowering (DIBL), voltage transfer curve (VTC) of subthreshold CMOS inverter, and NM degradation due to inclined sidewalls have been calculated using the developed models. According to the scaling theory, the minimum ${L}_{g}$ for a NM degradation of 5 mV is 30.5 nm corresponding to $\theta =0^\circ $ , and 42.7 nm at $\theta $ = 30° for ${H}_{Fin}$ = 20 nm. [ABSTRACT FROM AUTHOR]

Thermal impedance is required to describe static and fast dynamic thermal behavior in silicon-on-insulator (SOI) devices. This study presents an empirical physical model, which accounts for gate length, for calculating the thermal impedance of multi-finger partially depleted (PD) SOI MOSFETs at room temperature. For the first time, the parameters of the model are obtained from measurements of ac conductance and the characteristic thermal frequency determination. The model shows decreasing thermal resistance and linearly augmented thermal capacitance with increasing gate length from 0.18 to 2.50 $\mu \text{m}$. Thus, thermal time constants of ~760 ns, extracted from a variety of gate lengths, are correctly predicted. [ABSTRACT FROM AUTHOR]

In solution-processed oxide thin-film transistors, postdeposition thermal processing significantly changes the film’s transport properties and is essential for high-performance devices. The mobility, bias stability, and trapping–detrapping related hysteresis are improved with higher processing temperatures, which is generally attributed to decreased concentrations of localized states that act as electron traps. Fabricating and characterizing 29 devices, we provide further experimental evidence that postdeposition processing, indeed, leads to enhanced channel electron mobility in sol–gel indium–zinc oxide TFTs, and on the basis of a simple model, we extract physical parameters that yield a quantitative assessment of the changes in the densities and the properties of the localized trap states. The data are obtained for sol–gel indium–zinc oxide thin films and TFTs subjected to thermal postdeposition processing from 300 °C to 500 °C. The extracted parameters indicate that the trap state densities in the bulk semiconductor and at the interface decrease by factors of 5 and 3, respectively. Furthermore, the localized states become shallower, and the band mobility increases with higher processing temperatures. [ABSTRACT FROM AUTHOR]

In this article, we present a compact model of metal–ferroelectric (FE)–insulator–semiconductor (MFIS) tunnel junction. Unlike the metal–FE–metal (MFM) structure with only one insulator layer, MFIS–FE tunnel junction (FTJ) contains two insulator layers and a semiconductor electrode. The complex structure makes it difficult to self-consistently solve the Poisson and charge equations. We report the first compact model of MFIS-FTJ to our knowledge. Previous modeling studies focused on numerical simulation, which is time-consuming and not applicable to circuit simulation. The presented compact model is suitable for commercial SPICE IC simulation. It includes a FE model that can capture polarization switching under arbitrary applied voltage, an insulator–semiconductor model that calculates the potential profile of the MFIS stack, and an analytical tunneling current model. We demonstrate that this model can be used to simulate and fit both n-type and p-type MFIS-FTJs. [ABSTRACT FROM AUTHOR]

In this work, a physics-based compact model for channel charges and drain current in nanosheet FETs is presented. The model follows the bottom-up approach. The channel charges are calculated using the 1-D density of states (DOS), which seamlessly scales up for devices with 2-D or 3-D DOS as the confinement reduces in a particular direction. The model uses full Fermi–Dirac (FD) statistics and requires only two additional fitting parameters. The accuracy of the model is confirmed by comparing it with data from in-house 2-D coupled Poisson–Schrödinger (PS) solver and Technology Computer Aided Tool (TCAD) simulations. The proposed model accurately predicts the subband energies, inversion charges, channel potential, and drain current for nanosheet FETs (NsFETs) with different dimensions and applied biases. [ABSTRACT FROM AUTHOR]

In this article, a novel tree-type channel reconfigurable field-effect transistor (RFET) is proposed to obtain improved ON-state performance. Compared with the conventional nanosheet (NS) channel structure, an additional interbridge (IB) channel is vertically intersected in tree-type RFET. Geometry parameters of IB and NS, along with various gate dielectric materials with fixed EOT, are investigated in the point of threshold voltage (${V}_{\text {TH}}$) and on-state current (${I}_{ {\mathrm {\scriptstyle{ON}}}}$). When high- ${k}$ gate dielectric is adopted, the large cross-sectional area of IB will provide a better ON-state characteristic because of the larger tunneling area. Compared with the conventional NS RFET, ${I}_{ {\mathrm {\scriptstyle{ON}}}}$ of tree-type RFET with IB width (${W}_{\text {IB}}$) = 5 nm, NS space (${S}_{\text {NS}}$) = 25 nm, and HfO2 gate dielectric is separately demonstrated to improve by 44.6% and 60.2% for n- and p-type program, while in the case of SiO2 gate dielectric, suitable size parameters should be selected to obtain an improved ON-state current because of the tunneling strength. The underlying physical mechanism is discussed in detail. [ABSTRACT FROM AUTHOR]

In this article, we investigate the self-heating effect (SHE) of the Complementary FET (CFET) device and propose a cross-coupled thermal network model. For the investigation of thermal behavior, the intra- and inter-device crosstalk of CFET is evaluated qualitatively through the defined crosstalk coefficient. The results indicate that CFETs have more severe intra-device thermal crosstalk, almost twice that of CMOS. Moreover, the vertical structure makes the heat dissipation path of CFET devices significantly different in the two transition states (inputs “1” and “0”). Based on the thermal behavior characteristics of CFET and the necessity of high-precision and rapid prediction of thermal characteristics of the devices, a thermal network model is proposed, which can quickly respond to the heat source and be extended at the array level. In the last part, we analyze the influence of load capacitance and operating frequency on the self-heating of CFET, and SHE-related reliability lifetime is predicted based on the lattice temperature obtained from the thermal network. The prediction results show that the bias temperature instability (BTI) lifetime of CFET degrades by 84% compared with standard CMOS. [ABSTRACT FROM AUTHOR]

The nanowire gate-all-around structure with the ultimate channel electrostatic integrity exhibits the best immunity to short channel effects and improved scaling capability compared with other multigate structures. In this article, both the tunneling current and capacitance models are developed simultaneously for nanowire tunneling field-effect transistors (FETs). Based on the same surface potential model, the developed current model and capacitance model share the common parameters and therefore can be easily integrated as a complete model for circuit-level simulations. Moreover, there is no iterative process involved during the model derivation indicating the models would be efficient for circuit simulations. The proposed models are also implemented into a circuit simulator with SPICE net-list to simulate the inverter, NAND, and NOR gates. Correct circuit behaviors obtained validate the model compatibility with the SPICE platform and usefulness for the further investigation of nanowire-based tunnel FET (TFET) circuits. [ABSTRACT FROM AUTHOR]

The popular Tung model for Schottky barrier inhomogeneity considers how low-barrier patches (embedded in a high barrier background) impact the diode current. However, Tung’s model fails to account for the image-force effect. We analyze how the image force alters the current through an inhomogeneous barrier and find that, in some circumstances, it will smooth the barrier, such that the current will effectively be that of a homogeneous diode. We also show that for a distribution of defect barriers and/or sizes, the diode current can be intermediate between that of a homogeneous diode and a diode dominated by the low-barrier patches. We calculate the parameter values associated with this transitional region. A survey of existing literature applications of Tung’s model shows that many diodes are actually operating in this transition region, where Tung’s equations are in error. We provide the corrected equations for this case and demonstrate their ability to model practical diode characteristics. [ABSTRACT FROM AUTHOR]

In this article, a novel machine learning regression-based single-event transient (SET) modeling method is proposed. The proposed method can obtain a reasonable and accurate SET model without introducing complex physical mechanisms, which are not suitable for circuit-level simulation, into the model. To capture the essential physics behind these current transients caused by SET in the circuit-level simulations, we collect plenty of SET current data under different conditions [e.g., different linear energy transfer (LET), different drain bias voltage, different strike position, etc.] to train the SET model. To show the effectiveness of the proposed modeling method, we build a SET pulse current model by learning SET current data of Semiconductor Manufacturing International Corporation (SMIC) 130-nm bulk CMOS obtained by TCAD simulation. A multilayer feedforward neural network is used to build the SET pulse current model and the built SET model takes into account the dependence of time, LETs, drain bias voltages, and strike positions. The results from the model are validated with the simulation from TCAD. The trained SET pulse current model is implemented as a Verilog-A current source in the Cadence Specter circuit simulator, and an inverter with five fan-outs is used to show the practicability and reasonableness of the proposed SET pulse current model for circuit-level single-event effect (SEE) simulation. [ABSTRACT FROM AUTHOR]

Emerging voltage reference generators (VRGs) are of great demand for low-power applications in recent years. However, keeping good linearity for VRGs in deep submicrometer process is still challenging. Negative capacitance field-effect transistor (NCFET) is an emerging device, which has been found with a negative differential resistance (NDR) phenomenon and has the potential to be applied in VRGs to optimize their linearity. Hence, the feasibility of using NCFET in an emerging ultralow-power (ULP) VRG is studied in this work. An empirical formula to describe NCFET’s NDR is proposed and verified by simulation through a compact SPICE model based on the Landau–Khalatnikov (LK) equation. By adjusting the strength of NDR of NCFET, its output differential resistance can be changed and cancel out the positive differential resistance (PDR) of CMOS transistor. Therefore, the proposed NCFET-based VRG achieves higher linearity. The simulation results show that the line regulation of the NCFET-based VRG decreases from 2.25%/V to 0.21%/V ($10\times $). [ABSTRACT FROM AUTHOR]

We present a physics-based circuit-compatible model for pH-sensitive field-effect transistors based on 2-D materials. The electrostatics along the electrolyte-gated 2-D-semiconductor stack is treated by solving the Poisson equation, including the site-binding model and the Gouy–Chapman–Stern approach, while the carrier transport is described by the drift-diffusion theory. The proposed model is provided in an analytical form and then implemented in Verilog-A, making it compatible with standard technology computer-aided design tools employed for circuit simulation. The model is benchmarked against two experimental transition-metal-dichalcogenide (MoS2 and ReS2)-based ion sensors, showing excellent agreement when predicting the drain current, threshold voltage shift, and current/voltage sensitivity measurements for different pH concentrations. [ABSTRACT FROM AUTHOR]

There is a growing consensus that the physics-based model needs to be coupled with machine learning (ML) model relying on data or vice versa in order to fully exploit their combined strengths to address scientific or engineering problems that cannot be solved separately. We propose several methodologies of bridging technology computer-aided design (TCAD) simulation and artificial intelligence (AI) with its application to the tasks for which traditional TCAD faces challenges in terms of simulation runtime, coverage, and so on. AI-emulator that learns fine-grained information from rigorous TCAD enables simulation of process technologies and device in real-time as well as large-scale simulation such as full-pattern analysis of stress without high demand on computational resource. To accelerate atomistic molecular dynamics (MD) simulation, we have done a comparison study of descriptor-based and graph-based neural net potential, and also show their capability with large-scale and long-time simulation of silicon oxidation. Finally, we discuss the use of hybrid modeling of AI- and physics-based model for the case where physical equations are either fully or partially unknown. [ABSTRACT FROM AUTHOR]

A machine learning (ML) aided device simulation of work function fluctuation (WKF) for 3-D multichannel gate-all-around silicon nanosheet MOSFET is presented. To establish the ML model, the random forest regressor (RFR) is explored to predict the characteristic variation of the explored device. The proposed ML-RFR algorithm for predicting the ${I} _{D}$ – ${V} _{G}$ curve shows the same degree of accuracy as device simulation and it also estimates the minimum required samples for the converged ML-RFR model, i.e., 330 samples. By using the root mean squared error value, error rate, and ${R} ^{{2}}$ score as the evaluation tools, our ML-RFR model infers with an ${R} ^{{2}}$ score of 99% and an error rate of less than 1%. The main objective of this work is to explore the possibility of ML model that can replace the device simulation to reduce the computational cost and drive energy-efficient devices. [ABSTRACT FROM AUTHOR]

This article presents the construction and analysis of a hybrid numerical method for the discretization of the convection-dominated nonlinear carrier transport process in semiconductor devices. In the construction of the method, the edge streamline upwind (SU) current density model is employed to overcome the nonconvergence brought by the nonlinear property of the current continuity equation, and the mixed finite volume-finite element method (FVFEM) is utilized to effectively extend the edge SU current density model to multidimensional applications. The proposed method is more reliable and flexible than the finite box (FB) method and streamline upwind Petrov–Galerkin (SUPG) method. The performance of several popular SU current density models is compared to find the optimal one. The proposed method is validated by comparing the calculated results with those calculated using commercial software. Based on the streamline upwind-finite volume-finite element method (SU-FVFEM), the finite element method (FEM), and the domain decomposition method (DDM), an in-house parallel computing electrothermal simulator is developed for large-scale semiconductor devices. The performance of the in-house developed parallel simulator is evaluated through simulations of a p-n junction diode and a 3-D bipolar transistor. The results demonstrated that the developed parallel simulator possesses good accuracy, applicability, and scalability. [ABSTRACT FROM AUTHOR]

We report the development of a process/device simulation platform to model superconductor electronics. The process simulator leverages the back-end modeling capabilities of Florida object-oriented process/device/reliability simulator (FLOOXS) and builds on the existing models to simulate processes specific to Josephson junction (JJ) fabrication. The device simulator uses the process generated models and computes the normal-state electrical properties of a Nb/Al-AlO/Nb JJ. It is used to predict key operational figures of merit and how they vary with changes in process models. By integrating the process and device simulation tools, this research aims to offer an environment for the simulation of JJ circuits. [ABSTRACT FROM AUTHOR]

We present, here, advanced density functional theory and nonequilibrium Green’s function (DFT–NEGF) techniques that we have implemented in our ATOmistic MOdeling Solver (ATOMOS) to explore transport in novel materials and devices, particularly in van der Waals (vdW) heterojunction transistors. We describe our methodologies using plane-wave DFT, followed by a Wannierization step, and a linear combination of atomic orbital DFT that lead to orthogonal and nonorthogonal NEGF models, respectively. We then describe in detail our nonorthogonal NEGF implementation including the Sancho–Rubio method and electron–phonon (e–ph) scattering within a nonorthogonal framework. We also present our methodology to extract e–ph coupling from first principles and include them in our transport simulations. Finally, we apply our methods to the exploration of novel 2-D materials and devices. This includes 2-D material selection and the dynamically doped FET for ultimately scaled MOSFETS, the exploration of vdW tunneling field-effect transistors (TFETs), in particular the HfS2/WSe2 TFET that could achieve high ON-current levels, and the study of Schottky barrier height and transport through a metal-semiconducting WTe2/WS2 vdW junction transistor. [ABSTRACT FROM AUTHOR]

We present an efficient numerical technique for the temperature-dependent TCAD analysis of semiconductor devices. The approach is based on the linearization of the physical model around a nominal temperature operating condition, and exploits the Green’s functions (GFs) of the physical model to estimate the device characteristics at a different temperature. Self-heating can also be accounted for through coupling an external thermal circuit, with no numerical overhead. In the static (dc) case, the thermal analysis can be readily implemented in TCAD tools, using GFs customarily used for the electron device noise and variability analyses. The proposed technique is also extended to the dynamic case, to model the temperature dependence of electron devices operating in large signal conditions. We provide an extensive validation of the GF-based thermal analysis, including simulations of a 22-nm FinFET and of an InGaAs HEMT with 250 nm gate length. In the dynamic case, we demonstrate the efficient thermal analysis of a medium power amplifier in a FinFET technology. [ABSTRACT FROM AUTHOR]

With the quasi-3-D scaling equation, quasi-3-D minimum channel potential, and drift-diffusion model, a unified subthreshold current model for junctionless multiple-gate (JLMG) MOSFETs including quadruple-gate (QG), triple-gate (TG), and omega-gate ($\Omega \text{G}$) devices is developed. With this subthreshold current model, the noise margin (NM) behavior of the subthreshold logic gate composed of JLMG MOSFETs is assessed. With the same cross-sectional area of the devices, the QG MOSFET provides the largest NM among the three devices due to its smallest scaling length. On the contrary, the TG MOSFET with the largest scaling length exhibits the smallest NM. The short-channel-degraded NM behavior can be similarly seen in these devices. In terms of design triangle (DT) of subthreshold logic gate, the QG MOSFET can provide the largest DT as opposed to the smallest one supplied by the TG device. The transistor strength balance (TSB) between p-type and n-type JLMG MOSFETs can be adjusted by tuning the gate work function to implement the optimum NM design. Finally, the impact of random doping fluctuation (RDF) on NM degradation is also discussed in this work. [ABSTRACT FROM AUTHOR]

This article presents a distributed analysis of 2-D plate capacitors with resistive top and bottom plates, which results in two coupled partial differential equations in two variables. The exact solutions for the input impedance of a rectangular capacitor are derived for several contacting scenarios. Using frequency power series analysis, we prove the resistance decoupling theorem: the effective (low frequency) series resistance of a plate capacitor is the sum of the effective resistances of the top and bottom plates considered separately. The exact effective resistance can be calculated by assuming a uniform vertical capacitive current flow between the two plates. Based on this theorem, the effective resistance for any contact scenario is derived. Our analysis also results in a geometry-dependent model for the intrinsic base resistance of BJTs that is more accurate than any previous model. [ABSTRACT FROM AUTHOR]

We present the physics and performance space of the tri-gate GaN junction high electron mobility transistor (Tri-JHEMT), a new tri-gate GaN device proposed recently. In Tri-JHEMTs, p-n junctions wrap around two-dimensional-electron-gas (2DEG) fins in the gate region. Our fabricated Tri-JHEMT demonstrates, for the first time, the kilovolt blocking capability at 150 °C in all tri-gate GaN high electron mobility transistors (HEMTs). Three-dimensional TCAD simulations were then calibrated with experimental devices and used to study p-GaN-based Tri-JHEMTs with various design parameters for a direct comparison with the industrial planar p-gate GaN HEMTs. Owing to the unique physics of the sidewall p-GaN/2DEG junction, the 2DEG distribution in junction tri-gates is very different from that in conventional tri-gates, enabling smaller gate capacitance and superior gate controllability. As a result, a lower resistance in the gated channel, a higher wafer 2DEG density, and a scaled gate length can be concurrently realized in normally-OFF Tri-JHEMTs. GaN Tri-JHEMTs designed for a wide range of voltage classes (15–1200 V) are predicted to enable a 15%–75% lower ON-resistance (${R}_{ \mathrm{\scriptscriptstyle ON}}$), 3–10-fold smaller ${R}_{ \mathrm{\scriptscriptstyle ON}}\cdot {Q}_{\mathrm {G}}$ (gate charge), and 45%–63% smaller ${R}_{ \mathrm{\scriptscriptstyle ON}}\cdot {Q}_{\mathrm {OSS}}$ (output charge) as compared with similarly rated planar p-gate HEMTs. Considering their fabrication compatibility with existing foundry process, Tri-JHEMTs show great potentials as the next-generation lateral GaN power switches. [ABSTRACT FROM AUTHOR]

The mobility degradation with channel length is examined from the viewpoint of electrostatic effects that alter not only the threshold voltage but also the transport properties. Even operated at low drain voltage, short MOSFETs are subject to a strong lateral electric field present over a significant portion of the channel. The lateral field, responsible for threshold voltage roll-off, causes a local degradation in the velocity and mobility of electrons and holes. The low-mobility regions located near the source and drain tend to merge in short devices, giving rise to an ineluctable mobility collapse that compromises the benefit of downscaling. This mechanism is fundamental and universal as it applies to all kinds of MOSFETs. A model of mobility collapse, totally different from existing theories, is proposed together with supportive numerical simulations. [ABSTRACT FROM AUTHOR]

We derive a complete set of expressions for the MOSFET gate and drain power spectral densities due to elastic and inelastic trapping/detrapping of channel carriers into the gate dielectric. Our calculations explain trapping/detrapping noise (TDN) in various FET operating regions and highlight trap’s position-dependent terms, often neglected in the literature, which are instead important for devices with thin gate dielectrics. Furthermore, we show that TDN has a contribution to the gate current noise, correlated with the drain current fluctuations and we highlight the role of the transfer function between channel charge fluctuations and drain current on the noise characteristics. The model expressions are carefully validated by comparison with 2-D and 3-D TCAD simulations of scaled MOSFETs with different architectures (bulk, fully depleted-silicon-on-insulator (FD-SOI), FinFET), channel, and gate materials. Besides shedding new light on TDN, the results could enable trap density extraction from experimental samples with improved accuracy and pave the way to complete and accurate compact models for TDN in MOSFETs. [ABSTRACT FROM AUTHOR]

We present and discuss explicit closed-form expressions for the saturation drain current of short-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) with gate oxide and interface-trapped charges, and including carrier velocity saturation, according to the generalized Enz–Krummenacher–Vittoz (EKV) MOSFET compact model. The normalized saturation drain current is derived as an explicit function of the normalized terminal voltages by solving the transcendental voltage versus charge equation using the Lambert ${W}$ function. Because this special function is analytically differentiable, other important quantities, such as the transconductance and the transconductance-to-current ratio, can be readily expressed as explicit functions of the terminal voltages. [ABSTRACT FROM AUTHOR]

A compact model approach to enhance the accuracy and facilitate the parameter extraction of trapping models is presented. The proposed model replaces the conventional superposition of discrete trapping time constants by a Gaussian distribution of a particular range of time constants. This approach reflects the physically non-constant energy levels of the trap distribution of surface, interface, and bulk traps. Also, we propose a new equivalent circuit that takes the time-dependent charging and discharging of traps into account. We show that our model reduces the model complexity by 52%. The model is verified against dynamic ON-state resistance (${\mathrm {R}}_{\text {DS}, \mathrm{\scriptscriptstyle ON}}$) measurements of a commercial 100-V gallium-nitride (GaN) power transistor in soft-switching operation. [ABSTRACT FROM AUTHOR]

The extremely low threshold voltage (${V}_{\text {TH}}$) of native MOSFETs (${V}_{\text {TH}}~\approx $ 0 V@300 K) is conducive to the design of cryogenic circuits. Previous research on cryogenic MOSFETs mainly focused on the standard threshold voltage (SVT) and low threshold voltage (LVT) MOSFETs. In this article, we characterize native MOSFETs within the temperature range from 300 to 4.2 K. The cryogenic ${V}_{\text {TH}}$ increases up to ~0.25 V (W/L = 10/ $10~\mu \text{m}$) and the improved subthreshold swing (SS) ≈ 14.30 mV/dec@4.2 K. The OFF-state current (${I}_{ \mathrm{\scriptscriptstyle OFF}}$) and the gate-induced drain leakage (GIDL) effect are ameliorated greatly. The step-up effect caused by the substrate charge and the transconductance peak effect caused by the energy quantization in different sub-bands are also discussed. Based on the EKV model, we modified the mobility calculation equations and proposed a compact model of large-size native MOSFETs suitable for the range of 300-4.2 K. The mobility-related parameters are extracted via a machine learning (ML) approach, and the temperature dependences of the scattering mechanisms are analyzed. This work is beneficial to both the research on cryogenic MOSFETs’ modeling and the design of cryogenic CMOS circuits for quantum chips. [ABSTRACT FROM AUTHOR]