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With experimental and numerical simulation, we report the origin of the performance enhancement in p-type SnO thin-film transistors (TFTs) due to fluorine plasma treatment (FPT). To study the effect of fluorination, using the reactive-ion-etching process, the devices are treated at various plasma powers upto 60 W. It is observed, through X-ray photoelectron spectroscopy and XRD measurements, that the plasma fluorination modifies the defect/trap states of SnO channel and SnO/HfO2 interface. These effects are introduced through density of state (DOS) model for SnO in numerical simulations, to understand the routes of electrical performance improvement. It is observed that the attributes of donor-like band-tail state and acceptor-like Gaussian defect states (Sn vacancies) are modified in overall DOS due to plasma fluorination. The treated device shows excellent electrical performances with high ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of ~107 and low substhreshold swing of ~ 100 mV/dec and field-effect mobility ( $\mu _{\text {FE}}$ ) of 2.13 cm2V−1s−1.

In this paper, we reported a ferroelectric HfAlO x negative capacitor transistor with gate-stress (GS) engineering. Compared to control device, the HfAlO x transistor with GS engineering percentage of $\text{I}_{ \mathrm{\scriptscriptstyle ON}}$ enhancement and 27% $\text{V}_{T}$ reduction under the assistance of the negative capacitance (NC) effect. The orthorhombic phase transition played a crucial role in realizing the NC effect. From the results of the material analysis, the theoretical Landau simulation and electrical measurement, we demonstrated that the GS is favorable for inducing orthorhombic phase crystallization of HfAlOx and stabilizing the NC effect, which shows the potential for the application of advanced technology node.

For the first time, we successfully demonstrated the dopant-free HfO2 negative capacitance (NC) transistor featuring a low gate-overdrive voltage and a nearly hysteresis-free sub-40 mV/dec swing. These excellent performances can be ascribed to the reduction of the monoclinic phase suppressed with the thickness scaling and gate stress engineering favorably rearranging oxygen vacancies to boost orthorhombic phase transition. The highly scalable and dopant-free NC transistor shows the potential for the application of advanced CMOS technology.

Achieving high latch-up immunity is critical for power-rail electrostatic discharge (ESD) clamp circuits in high-voltage (HV) integrated circuit products. To investigate how shunt resistance affects the transmission line pulsing current–voltage characteristics of resistance-triggered stacked silicon controlled rectifiers (SCRs), a lateral SCR (LSCR) and a modified LSCR were combined in several SCR stacked structures with various shunt resistances. Compared with in tradition stacked ESD cells, the snapback margin of the SCRs does not expand and can even be reduced. A high holding voltage of 33.4 V is achieved using the resistance-triggered stacked SCR technique in a $0.11~\mu \text{m}$ 32-V HV process. A trigger voltage of approximately 51 V and a failure current of 3.3 A is achieved in this experiment. According to theorem analysis based on a voltage decoupling equation, the minimum trigger voltage can probably be further reduced to 46 V by using the resistance-triggered stacked SCR technique. This paper can offer a simple guideline for designing ESD protection circuit using the resistor-triggered SCRs stacking structure.

In this brief, we reported a ferroelectric versatile memory with strained-gate engineering. The versatile memory with high-strain-gate showed a >40% improvement on ferroelectric hysteresis window, compared to low-strain case. The high compressive stress induced from high nitrogen-content TaN enhances monoclinic-to-orthorhombic phase transition to reach stronger ferrolectric polarization and lower depolarization field. The versatile memory featuring ferroelectric negative capacitance exhibited excellent transfer characteristics of the sub-60-mVdec subthreshold swing, ultralow off-state leakage of $\mu \text{m}$ and $> 10^{\mathsf {8}}$ on/off current ratio. Furthermore, the ferroelectric versatile memory can be switched by ±5 V under 20-ns speed for a long endurance cycling (~1012 cycles). The low-power operation can be ascribed to the amplification of the surface potential to reach the strong inversion and fast domain polarization at the correspondingly low program/erase voltages.

This paper presents a parallel plate-type field emission device of potassium hydroxide-doped electrochemically reduced graphene oxide (GO) manufactured using highly oriented pyrolytic graphite through electrochemical exfoliation. The material properties of the GO were tested through Raman spectroscopy, X-ray diffraction, and X-ray photoelectron spectroscopy. The optimal electron emission characteristics of the device were as follows: turn-on field = 2.03 V/ $\mu \text{m}$ , field emission current $= \,\, 16.4~\mu \text{A}$ , and field emission enhancement factor = 8377. At an emission peak wavelength of 563.7 nm, the optimal device had a light flux of 4.21 lumens and an illumination of 140.3 lux. These properties can be utilized in various optoelectronic devices, such as nanoelectronics devices, sensors, electrochemical systems, and energy storage devices.

The deep trench (DT) process module shows a strong impact on SiGe BiCMOS n-p-n array yield. DT liner oxidation introduces large tensile stress at the top of DT corners and in the vicinity of intrinsic SiGe base/collector regions. The increased tensile stress can result in dislocations in silicon. By replacing the 100-nm wet oxidation DT liner with a TEOS deposition liner, n-p-n array collector-emitter leakage yield can be improved from 64% to 94% in the investigated 0.18-μm DT SiGe BiCMOS process, comparable to the yield of a non-DT low-cost SiGe BiCMOS process.

Barium-doped TiO2 films deposited on GaN layers at low temperature through a simple liquid phase deposition method is investigated. The use as a gate dielectric in AlGaN/GaN metal-oxide-semiconductor high-electron mobility transistors (MOSHEMTs) is also demonstrated. The electrical characteristics of the MOS structure on n-doped GaN show that the leakage current density is about 5.09 × 10-9 A/cm2 at 1 MV/cm, and the breakdown field is more than 13 MV/cm. The maximum drain current density of the AlGaN/GaN MOSHEMTs is higher than that of HEMTs, in which a wider gate voltage swing and a lower subthreshold swing (110 mV/decade) are obtained. The gate leakage current density is significantly improved, and the gate pulse measurement shows that the current collapse is more suppressed for MOSHEMTs.

This brief presents high-performance Ge n-MOSFETs with good high-field mobility of 218 cm2/V · s at 0.5 MV/cm, low subthreshold swing (SS) of 108 mV/dec, small equivalent oxide thickness (EOT) of 1.6 nm, low 7 × 10-10 A/μm OFF-state leakage, small bias temperature instability of 31 mV at 1.2 V overdrive and 85°C, and full process compatibility with current very large-scale integration fabrication. These are one of the best SS and high-field mobility data among gate-first Ge n-MOSFETs using epitaxial Ge on 6-in Si wafer and proper high-κ LaAlO3 dielectric without using an interfacial layer. Using a different high-κ HfAlO gate dielectric, the Ge n-MOSFETs showed poor leakage, large flatband voltage shift, and degraded EOT.

TiO2 films deposited on GaN layers at room temperature through a simple and low-cost liquid-phase deposition (LPD) method are investigated and served as gate dielectrics in AlGaN/GaN MOSHEMTs. The electrical characteristics of the MOS structure on n-doped GaN show that the leakage current is about 1.01times10-7 A/cm2 at 1 MV/cm and that the breakdown field is more than 6.5 MV/cm. The maximum drain current density of MOSHEMTs is higher than that of conventional HEMTs, and a wider gate voltage swing can also be observed. The maximum transconductance and threshold voltage almost maintain the same characteristics, even after inserting a dielectric layer between the gate metal and the 2DEG channel by using TiO2 as a gate dielectric. The gate leakage current density is significantly improved, and the bias stress measurement shows that current collapse is much suppressed for MOSHEMTs.

In this paper, we present a new and analytical drain current model for submicrometer SOI MOSFET's applicable for circuit simulation. The model was developed by using a two-dimensional (2-D) Poisson equation, and considering the source/drain resistance and the self-heating effect. Using the present model, we can clearly see that the reduction of drain current with the parasitic series resistance and self-heating effect for typical SOI devices. We also can evaluate the impact of series resistance and self-heating effects. The accuracy of the presented model has been verified with the experimental data of SOI MOS devices with various geometries.

In this paper, we present a new, analytical, and physics-based drain current model for both submicrometer and deep submicrometer MOSFET's. The model was developed by starting from a two-dimensional (2D) Poisson equation and using the energy balance equation. Using the present model, we can clearly see that the drain current increases with decreasing channel length due to a larger average channel mobility at shorter channel length. The formulas for the saturation drain voltage and the drain current can be reduced to their corresponding well-known formulas in the submicrometer range. The accuracy of the presented model has been verified with the experimental data of metal-oxide-semiconductor (MOS) devices with various geometries.