Search

The dielectric screening property of a semiconductor is very crucial for the electrical characteristics of a MOSFET, and which can be described mathematically by Poisson equation via the permittivity. While the theory and experiments have corroborated the permittivity reduction of nanoscale Si, this paper studies the electrical characteristics of MOSFETs considering the reduced channel permittivity by quantum transport simulations. It is found that the channel permittivity reduction may mitigate the short-channel effects, showing subthreshold swing improvement and threshold voltage shift of MOSFETs in nanoscale. Compared to quantization effects, the positive and negative impacts of the channel permittivity reduction on the devices in particularly nanoscale have been investigated. This paper elucidates the necessity of considering semiconductor permittivity reduction for nanoscale device design and simulations. [ABSTRACT FROM AUTHOR]

This paper clarifies the correct transmission mechanism, misattributed in the previous research, of a hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) device. Complete drain current–gate voltage (${I}_{\text {D}}$ – ${V}_{\text {G}}$) transfer characteristics including the forward and backward gate sweeps (gate voltage carried out in the OFF-state $\to $ on-state and the ON-state $\to $ OFF-state) are performed, and the physics models of an energy-band schematic are clearly explained. This paper reveals that the ${I}_{\text {D}}$ – ${V}_{\text {G}}$ curve stretch-out behavior of the subthreshold region is due to the leakage of the Poole–Frenkel region. At the Poole–Frenkel regions, electrons transfer to the drain terminal, and holes remain in the valance band of the a-Si:H bulk. The remaining holes represent the positive voltage and cause the electron barrier height lowering. This causes an increase in subthreshold current of the subthreshold region. Finally, three experiments are performed to prove the correctness of these models, and the a-Si TFTs device improvement methods will be proposed to enhance the stability and performance of product of the a-Si TFTs. [ABSTRACT FROM AUTHOR]

In order to better predict the high-frequency switching operation of transistors in power converters, parasitic elements of these devices such as resistances, inductances, and capacitances must be accurately evaluated. This paper reports on the characterization of a gallium nitride (GaN) packaged power transistor using S-parameters in order to extract the device parasitics. Because the transistor is packaged, a calibration technique is carried out using specific test fixtures designed on FR4 printed circuit board (PCB) in order to get the S-parameters in the transistor plane from the measurement. The proposed method is suitable for a wide range of power devices. In this paper, it is applied to an enhancement-mode GaN high electron mobility transistor (HEMT). The impact of junction temperature on drain and source resistances is also evaluated. According to characterization results, equation-based modeling is proposed for the nonlinear parameters. The extracted parasitic elements are compared with reference values given by the device manufacturer. [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel reconfigurable ferroelectric FET (R-FEFET), which can reconfigure its operation between volatile and nonvolatile modes during run-time by dynamically modulating its hysteresis. The R-FEFET comprises of two gates with ferroelectric (FE) in both the gate stacks. One of these terminals serves as a regular gate, while the other is used as a control to introduce reconfigurability. Employing Landau–Khalatnikov equation-based FEFET model, we extensively analyze the device characteristics in both FinFET and planar technologies. We show that by changing the control voltage between 0 and 1 V, the hysteresis width (HW) can be modulated between 1.1 and 0.3 V. In addition, we show the device characteristics and advantages that R-FEFETs possess to overcome the drawbacks encountered with gate leakage in standard FEFETs. The hold margins in the nonvolatile mode of R-FEFETs increase by ~ $10\times $ with respect to standard FEFETs, and the drive current strengths in the volatile mode show 13% improvements when compared to standard FETs. Using the proposed R-FEFETs, we examine a low-power nonvolatile memory design in Part II of this paper. [ABSTRACT FROM AUTHOR]

In this response, we show that the paper by Kim et al. by our group has a different research purpose and uses different modeling processes, which was not described in the previous work by Ortiz-Conde et al. The comments issued by Ortiz-Conde et al., who claim that our paper corresponds to a particular case of their previous work, are in our opinion overgeneralized. Differences compared to Ortiz-Conde’s previous work are discussed in detail. We also explain how the problem on threshold voltage pointed out by Ortiz-Conde et al. can be solved through a semiempirical method from measured data. [ABSTRACT FROM AUTHOR]

An introduction is presented in which the editor discusses various reports within the issue on topics including role of simulation technology, application of electrical circuit simulations in hybrid vehicle development, and Insulated Gate Bipolar Transistor (IGBT).

A Special Section in the IEEE Transactions on Semiconductor Manufacturing, May 2014: After nearly three decades of research and development, wide band gap semiconductors (e.g. SiC and GaN) are ripe for high-volume applications in power electronics, communication, sensors, solid-state lighting, and photovoltaics. However, there are significant manufacturing challenges that must be overcome before large-scale manufacturing can take place. Fundamental issues pertaining to high defect density in the material, proper yield estimation and metrology techniques, and focus on "applications-driven" manufacturing are essential in order to advance the manufacturing of wide band gap (WBG) semiconductors. The IEEE Transactions on Semiconductor Manufacturing solicits original papers addressing the challenges and opportunities in manufacturing ofWBG semiconductor devices. Deadline for Receipt of Papers is July 31, 2013. [ABSTRACT FROM AUTHOR]

A vertical ultrathin channel formation process for a vertical type double-gate (DG) MOSFET is proposed. Si wet etching using an alkaline solution has newly been found to be significantly retarded by introducing ion bombardment damage. We have also found that the ion bombardment-retarded etching (IBRE) is independent of ion species and the implanted impurities can easily be transferred to be the dopants for source and drain regions of MOSFETs. By utilizing the IBRE, vertical type DG MOSFETs with a 12-nm-thick vertical channel were fabricated successfully. The fabricated vertical DG MOSFETs clearly exhibit the unique advantage of DG MOSFET5, i.e., high improvement of short-channel effect immunity by reducing the channel thickness. Thanks to the ultrathin channel, very low subthreshold slopes of 69.8 mV/dec. for a p-channel and 71.6 mV/dec for an n-channel vertical DG MOSFET are successfully achieved with the gate length of 100 nm. [ABSTRACT FROM AUTHOR]

In negative capacitance field-effect transistors (NCFETs), drain current may decrease with increasing ${V}_{\mathrm {ds}}$ in the saturation region, leading to negative differential resistance (NDR). While NDR is useful for oscillator design, it is undesirable for most analog circuits. On the other hand, the tendency toward NDR may be used to reduce the normally positive output conductance ( ${g}_{ \mathrm {ds}}$ ) of a short-channel transistor to a nearly zero positive value to achieve higher voltage gain. In this paper, we analyze the NDR effect for NCFET in the static limit and demonstrate that it can be engineered to reduce ${g}_{\mathrm {ds}}$ degradation in short-channel devices. Small and positive $g_{\mathrm{ ds}}$ is achieved without compromising the subthreshold gain, which is crucial for analog applications. The 7-nm ITRS 2.0 FinFET with 0.7 V ${V}_{\mathrm {dd}}$ is used as the baseline device in this paper. [ABSTRACT FROM AUTHOR]

This paper presents a CMOS image sensor (CIS) utilizing a noise-shaping successive-approximation register analog-to-digital converter (SAR ADC) incorporating the delta-readout scheme. While the noise-shaping SAR ADC with a proposed two-tap passive finite-impulse response (FIR) filter improves effective resolution, the delta-readout scheme reduces its power consumption. A prototype 1920 x 1440 pixel CIS was fabricated in a 90-nm CIS process. A single-channel readout SAR ADC occupying an area of 22.4 µm x 715 µm was implemented for reading out 16 columns of pixel array, consuming 437 µW. Owing to the proposed noise-shaping SAR ADC with oversampling ratio of 16, this paper achieves a noise reduction of 14 dB compared with the noise of a conventional SAR ADC. The delta-readout reduces the power consumption of the SAR ADC by 10% due to the high hit rate of the full high definition image format. The measured differential nonlinearity of the ADC is +0.77/-0.54 LSB and the integral nonlinearity is +0.81/-0.5 LSB. The prototype CIS consumes a total power of 64 mW and achieves a dynamic range of 66.5 dB and a figure of merit of 127 µV·nJ at a data rate of 138 Mpixels/s. [ABSTRACT FROM AUTHOR]

In this paper, a p-channel vertical 4H-silicon carbide (SiC) MOSFET (SiC p-MOSFET) has been fabricated successfully for the first time as a potential candidate for the complementary inverter application. The static characteristics and the robustness, including short circuit and avalanche capabilities of the p-MOSFET, are experimentally tested. Moreover, the comparison between the p-MOSFET and similar rating n-MOSFET is carried out. The short-circuit capability is 15% higher than that of the n-channel MOSFET. Furthermore, this paper also provides the physical insights into the failure mechanism during the short-circuit transient of the p- and n-MOSFET. Meanwhile, an electro-thermal analytical model is proposed to explain the thermal distribution during this transient. Last, the avalanche withstand time of the fabricated SiC p-MOSFET is experimentally demonstrated to be 27% higher than that of the n-channel one. It is concluded that the SiC p-MOSFET could be a competitive power switch applicable for high-frequency complementary inverters. [ABSTRACT FROM PUBLISHER]

Conventionally, integrated drain-extended MOS (DeMOS) like high-voltage devices are designed while keeping only performance targets for a given application in mind. In this paper, for the first time, performance and reliability codesign approach using 3-D TCAD has been presented for various superjunction (SJ) type DeMOS devices. In this context, how to effectively utilize the SJ concept in a DeMOS device for System on Chip applications, which often has stringent switching and RF performance targets, is explored in detail in this paper. Moreover, design and reliability tradeoffs for switching and RF applications are discussed, while considering two unique sets, one with fixed breakdown voltage and other with fixed ON-resistance. Finally, hot carrier generation, safe operating area concerns, and electrostatic discharge physics are explored and compared using 3-D TCAD simulations. [ABSTRACT FROM PUBLISHER]

Due to the rapid advances taking place in the development and application of GaN electronics, there is an immediate need to take cognizance of the recent technological improvements and bring the potential and opportunities that exist in the area to a wider device community. The primary goal of this special issue is, therefore, to put together works in different aspects, including modeling, design, technology, characterization and applications so that this special issue will not only be of great archival value but also attract new researchers into this area for Digital Object Identifier 10.1109/TED.2013.2278653 further accelerating the application of III-N devices in building reliable, cheaper, and high-performance electronic systems. The papers collected in this special issue have been grouped into six topics. They are: 1) Fabrication and characterization of GaN-based devices. 2) High power GaN HEMTs for power switching applications. 3) High speed GaN HEMTs for RF applications. 4) Reliability and parasitic issues in GaN HEMTs. 5) Simulation-based development of GaN HEMTs devices. 6) GaN-based low noise amplifiers and gate drive circuits. [ABSTRACT FROM AUTHOR]

This paper investigates the impact of quantum capacitance on the intrinsic inversion-capacitance ( C\mathrm{ inv}) characteristics of high-mobility multigate III–V-on-insulator nMOSFETs through a numerical simulation corroborated by the theoretical calculation. Nonmonotonic C\mathrm{ inv} characteristics stemming from the energy dependence of 1-D density-of-states and significant C\mathrm{ inv} degradation due to quantum capacitance have been found in trigate In0.53Ga0.47As and InAs devices based on the ITRS 2018–2024 technology nodes. This paper indicates that, to compensate the excess inversion-charge ( Q\mathrm{ inv} ) loss due to quantum capacitance, the needed mobility gain of the trigate InGaAs and InAs devices (against the Si counterparts) should be at least $\sim 3\times $ and $\sim 4\times $ , respectively. This paper also suggests that the quantum-capacitance-induced Q\mathrm{ inv} loss can be mitigated by raising the fin aspect ratio of the III–V multigate device. [ABSTRACT FROM AUTHOR]

A call for papers for 2014 IEEE International Reliability Physics Symposium on topics related to circuits and products and devices process and materials reliability.

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

The instability of amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) under ultraviolet (UV) light was thoroughly investigated in this paper. Unlike in a darkened state, an off-state leakage current can be found in the dual-sweep I–V transfer curve of a-IGZO TFTs under UV light illumination. Furthermore, despite the same UV light condition, the forward sweep and reverse sweep show different I–V curves, representing two different physical mechanisms. First, the subthreshold swing degradation and threshold voltage shift to the negative direction in the forward sweep are due to the total channel barrier lowering and can be confirmed by changing the light exposure region. Second, in the reverse sweep, the suggested back-channel leakage current can be controlled by dual-gate TFTs. UV light exposure of the metal–insulator–semiconductor–metal structure verifies that the off-state leakage current passes through the back channel in a reverse sweep. Finally, the physical mechanism links between forward and reverse sweeps have comprehensive interpretation in this paper. [ABSTRACT FROM AUTHOR]

In this paper, we have developed a physics-based analytical model for the electrical characteristics of passivated silicon carrier-selective contact (CSC) solar cells and validated it with numerical simulations. The model comprises analytical solutions of: 1) the Poisson equation, accurately capturing the level of inversion and accumulation at the crystalline silicon (c-Si) layer interfaces, and 2) the recombination current capturing the various recombination mechanisms at work in the solar cell. The calculations establish that CSC solar cells have the potential to achieve an efficiency greater than 26% even when both c-Si interfaces have realistic SRV values of 100 cm/s. The model helps illustrate the physics underlying the performance of CSC solar cells for variation in key device parameters such as surface recombination velocities, bulk lifetime, contact layer doping, and amorphous silicon (a-Si) thickness amongst others. By circumventing the need for resource-intensive numerical simulations, the analytical model described in this paper can assist in the design and development of high-performance CSC solar cells. [ABSTRACT FROM AUTHOR]

Recent studies of electroluminescent cooling (ELC) in III–V structures demonstrate the need to better understand the factors affecting the efficiency of light emission and energy transport in light-emitting diodes (LEDs). In this paper, we establish the physical and operational requirements for reaching the efficiencies needed for observing ELC in the III–V intracavity double-diode structures at high powers. The experimentally validated modeling framework used in this paper, coupling the drift-diffusion charge transport model with a photon transport model, indicates that the bulk properties of the III–V materials are already sufficient for ELC. Furthermore, the results suggest that the bulk power conversion efficiency of the LED in the devices, which allowed the experimentally measured record high coupling quantum efficiency of 70%, already exceeds 115%. However, as shown here, direct observation of ELC by electrical measurements still requires a combination of a more efficient suppression of the nonradiative surface recombination at the LED walls and the reduction of the detection losses in the photodetector of the intracavity structures. [ABSTRACT FROM AUTHOR]

To effectively solve the crosstalk issue in high-density crossbar array (CBA), high rectifying characteristics should be introduced in the resistance random-access memory (ReRAM) device, and in-depth understanding of the affecting factors on rectifying properties is essential for the large-scale application of ReRAM. In this paper, a high-performance self-rectifying device with CMOS compatible Pd/HfO2/TaOx/Ta structure was demonstrated in a 1-kb CBA. Forming-free, self-compliance, and high uniformity characteristics were successfully achieved. By modulating the thickness of the HfO2 rectifying layer, the rectifying ratio of device could be achieved as high as $\sim 2\times 10^{\textsf {3}}$ under ±3 V at low-resistance state (LRS). It was also experimentally confirmed that the selected unit cell in high-resistance state (logically the “ OFF” state) was stably readable when it was surrounded by unselected LRS (logically the “ ON” state) cells, in an array of up to $32 \times 32$ cells. Furthermore, a model based on interfacial barrier modulation and defects trapping/detrapping was proposed to elucidate the impact of the dielectric thickness on the self-rectifying characteristics of the device. The results presented in this paper provide a great potential for selector-free high-density memory applications. [ABSTRACT FROM AUTHOR]

The minimum specific ON-resistance $\text{R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ of the semisuperjunction (semi-SJ) device is realized in this paper. Based on the similar SJ optimization method in our previous works, the minimum $\text{R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ of the semi-SJ is searched by optimizing both the semi-SJ and the N-buffer regions. The proposed design formulas give the optimized doping concentration $\text{N}_{\textsf {SJ}}$ of the semi-SJ region, doping concentration $\text{N}_{\textsf {B}}$ , and length $\text{L}_{\textsf {B}}$ of the N-buffer region, respectively. As examples, 1000- and 1500-V semi-SJ devices are designed with the formulas. The calculated results are in a good agreement with the simulations. The comparisons between the simulations and the existing experiments demonstrate that the optimization in this paper realizes lower $\text{R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ under the same breakdown voltage $\text{V}_{\textsf {B}}$ even with a shorter SJ length. [ABSTRACT FROM AUTHOR]

In this paper, we propose a model for estimating short-channel effects (SCEs) in the shell-doped double-gate junctionless (JL) MOSFET. The main emphasis of this paper is to estimate SCEs by effectively capturing source/drain (S/D) extensions beyond the gate edges for different values of undoped core thickness (${T}_{\textsf {core}}$), shell doping (${N}_{\textsf {d}}$), gate length (${L}_{\textsf {g}}$), and gate (${V}_{\textsf {gs}}$) and drain (${V}_{\textsf {ds}}$) biases in subthreshold regime. The threshold voltage (${V}_{\textsf {th}}$), drain-induced barrier lowering and subthreshold swing (${S}$), extracted from transfer characteristics, are in good agreement with the simulation results. Results highlight the utility of shell doping and core thickness to provide an additional degree of freedom to control SCEs. The proposed model can be useful in estimating SCEs and optimizing core–shell JL architecture for low-power applications. [ABSTRACT FROM AUTHOR]

We demonstrate, for the first time, resistive RAM (RRAM) arrays where each cell can store 3 bits. Such full array-level demonstration is possible through special techniques (e.g., that exploit RRAM-specific characteristics of variations in cell resistances), presented in this paper, which efficiently allocate resistance range corresponding to each bit combination (required for proper write operation) while maintaining appropriate sensing margin (required for proper read operation). Our techniques are not restricted to 3 bits-per-cell only (and, in this paper, we demonstrate 2 bits-per-cell at the array level as well). Our measured results are based on multiple 4 Kbit arrays of 1T1R HfOx-based RRAM integrated in the back end of the line of 130-nm silicon CMOS technology. We achieve 3 bits-per-cell (2 bits-per-cell) RRAM with 11 (3) programing iterations on average. [ABSTRACT FROM AUTHOR]

In this paper, the threshold voltage characteristics of silicon nanowire metal–oxide–semiconductor field-effect transistor (MOSFET) with a double-layer gate structure are presented. This type of device is considered to be the most promising application of nanodevice in ultralarge-scale integration, due to several advantages such as similar operation principle as the junctionless nanowire transistor, the screening effect of the upper gate (UG) to shield the lower gate MOSFETs from external electromagnetic disturbance, the tradeoff between the short channel and the thick-gate oxide layer, and the compatible fabrication process with the conventional MOS technology. In this paper, the relations of threshold voltage versus the gate length, the UG bias, the substrate bias, the drain bias, and the temperature are measured and analyzed. Moreover, the penetration effect of the UG electric field is proposed to interpret the short-channel characteristics of the device, and a piecewise curve model is presented to reveal the underlying physics of the relation of the threshold voltage versus the drain bias. The double-layer gate structure technology enables the design of many devices, such as small-signal analog circuit units, single-electron devices, and quantum bit cells. [ABSTRACT FROM AUTHOR]

This paper presents a new approach for compact modeling of aging and radiation effects for MOS transistors including process variation and environmental influences. This approach can be used in common design flows for analog integrated circuits. Moreover, the aging behavior of whole circuits can be analyzed without the need for abstractions or extrapolation. Only one common physically motivated transistor parameter is used in order to model radiation and degradation mechanisms. [ABSTRACT FROM AUTHOR]

Magnetic tunnel junctions (MTJs) with low switching current, high thermal stability, and small device size are strongly preferred for low-power, high-reliability, and high-density spintronic memory and logic applications. The research of MTJs from shape in-plane magnetic anisotropy to interfacial perpendicular magnetic anisotropy (i-PMA) has successfully paved the way down to 20-nm scale, below which, however, the i-PMA approach reaches a physical limit in sustaining sufficient thermal stability while achieving low-power spin transfer torque switching. Recently, studies have been reported a new approach to pave the way toward sub-10-nm MTJs satisfying the requirements by revisiting shape perpendicular magnetic anisotropy (s-PMA). In this paper, we present a compact model of the sub-10-nm s-PMA MTJ device, which captures both the static and dynamic physical behaviors. This model is SPICE-compatible for hybrid MTJ/CMOS circuit designs. This paper is expected to push forward the development of sub-10-nm-scale MTJ-based spintronic memory and logic circuits. [ABSTRACT FROM AUTHOR]

This paper presents the 2-D numerical simulation results of single-event burnout (SEB) in 4H-SiC junction barrier Schottky (JBS) diode by low carrier lifetime control (LCLC) for the first time. We investigate the SEB performance based on an 1800-V JBS structure and find that the most sensitive ion’s strike position is the middle of junction spacing because of the punchthrough of the electric field at anode contact. Then, the SEB hardening mechanism of LCLC is studied in this paper that the double-sided peak electric field can be effectively improved which results in a significantly decrease of maximal temperature. For the incident particle with different linear energy transfer values, we find that the SEB threshold voltage can be substantially enhanced when the carrier lifetime ($\tau $) is under a certain value. In addition, the basic characteristics with LCLC are discussed that the forward and reversed characteristics are hardly affected. [ABSTRACT FROM AUTHOR]

The p-n junction is the fundamental building block for electronics and photonics applications. In a conventional p-n junction, the performance parameters cannot be tuned due to the fixed doping level after ion implantation. In this paper, reconfigurable p-n or n-p junctions were built based on the ambipolar black phosphorus (BP) and other 2-D materials, namely, graphene and hexagonal boron nitride (h-BN). High-quality graphene/h-BN/BP/h-BN sandwich device was created by the dry transfer method in an inert environment. Graphene serves as the local back gate, which can tune BP partially into either n-type or p-type material. The rest of the BP channel can be controlled by the back gate. The BP encapsulated device can enable the high performance of the ideality factor down to 1.08 (p-n junction) and 1.18 (n-p junction). The device developed in this paper has a more balanced ideality factor than previously reported reconfigurable WSe2 and BP devices. By tuning the back gate and graphene gate, the BP device can be tuned into four operational quadrants, namely, n-n, n-p, p-n, and p-p junctions. Moreover, the hole mobility of BP is up to 404 cm2/ $\text {V}\cdot \text {s}$ at room temperature. Our work shows that the BP heterostructure is very promising for high-speed reconfigurable logic functions and circuits. [ABSTRACT FROM AUTHOR]

Esaki diodes based on interband tunneling have the characteristics of negative differential resistance (NDR) and ultrafast transient time, which lead to broad applications including oscillators, multivalue memories, and terahertz detectors. In this paper, we present the first demonstration of Esaki diodes based on 2-D/3-D heterojunctions—more specifically, chemical vapor deposition MoS2 on degenerately doped silicon. As compared to traditional 3-D heterostructures, these 2-D/3-D heterostructures have the following advantages: dislocation-free 2-D crystals even when the lattices are mismatched, dangling bond-free surface, and capability for large-scale synthesis at low cost. In this paper, monolayer, bilayer, and trilayer MoS2 are synthesized directly on degenerated Si substrate, forming the ultraclean heterostructures without surface contamination from tape and resist. Based on these pristine heterostructures, we are able to observe prominent NDR effect at room temperature. This NDR effect is attributed to the degenerately p-type doping in silicon and the natural n-type doping in MoS2. We also found that the peak voltage corresponding to the local maximum tunneling current depends on the MoS2 thickness. While MoS2 is changing from the monolayer (0.7 nm) to bulk (9.5 nm), the peak voltage increases from 0.8 to 1.6 V. This phenomenon can be explained by the energy-level differences between the monolayer and bulk MoS2. This paper provides the experimental groundwork for the synthesis of transition metal dichalcogenides on degenerately doped Si substrates and opens up new and exciting opportunities for electronic applications of 2-D/3-D heterostructures. [ABSTRACT FROM AUTHOR]

This paper analyzes the performance of mosaic nonimaging passive infrared (PIR) sensors fabricated by the CMOS–SOI–MEMS technology. The elementary sensor, forming a subpixel, is a thermally isolated nanomachined CMOS transistor, dubbed TMOS, operating at subthreshold. The mosaic uncooled PIR sensors are composed of several TMOS subpixels, which are electrically connected, either in parallel or in series as well as a combination of both options. These mosaic sensors, which are manufactured by nanofabrication methods, exhibit enhanced performance and robust manufacturing on wafer level. The overall figures of merit of these sensors, which are modeled in this paper, indicate why they are most suitable for consumer electronics, including smart homes, wearables, Internet of Things as well as mobile applications. [ABSTRACT FROM AUTHOR]

In this paper, we study the switching behavior of silicon-on-insulator light-emitting diodes (LEDs). Through the comparison of various device geometries, we establish the dimensional dependence of the switching speed of the LED. TCAD simulations are in line with the experimental results. Our findings indicate that ON–OFF keying up to GHz frequencies should be feasible with such diodes, although a design optimized for higher frequency operation will exhibit a reduced light emission efficiency. [ABSTRACT FROM AUTHOR]

It is well known that there is a critical Sn content for a GeSn alloy, at which the conduction band edges at ${L}$ and $\Gamma$ symmetry points are aligned in energy. For GeSn tunnel FET (TFET) simulations, with a given donor concentration, this paper reveals that simulations neglecting the multivalley and nonparabolic band structure would incorrectly predict the subthreshold slope (SS) and the off-currents. We highlight the indispensability of the consideration of the multivalley band structure of GeSn for TFET simulations. This paper provides the required parameters, which may be useful for numerical simulations of other optoelectronic and electronic GeSn devices. [ABSTRACT FROM AUTHOR]

This paper demonstrates a novel nanofabrication technology for producing high-density gated molybdenum (Mo) field-emitter array (FEA) based on modified nanosphere lithography (NSL). The arc-shaped side wall of gate apertures introduced by the conventional NSL process put obstacles in the formation of sharp cone-type emitters. In this paper, a two-method solution was employed to facilitate the realization of gate apertures with sharper cutting side wall which are beneficial for the formation of sharper gated Mo emitters. One method was softening nanosphere to enlarge the contact area between nanosphere and substrate. The other was optimizing gate film deposition conditions to dramatically reduce the diffraction effects. Due to the improvements in the geometrical shape of gated Mo emitters, a low-voltage working high-density gated Mo FEA was demonstrated in this paper. This is the first observation of remarkable electron emission from high-density gated Mo FEA fabricated using such as low-cost, high-throughput, and high-efficiency technique which is expected to substantially overcome the challenges in the traditional fabrication process and promotes the low-cost and large-area application of high-density gated field-emitter devices. In addition, the novel nanofabricating method is expected to offer a simple and scalable route which allows fabrication of many gated field-emission devices. [ABSTRACT FROM AUTHOR]

In this paper, the pinning process of pinned photodiodes (PPDs) is described by a new analytical model, assuming the PPD to be composed of inner and junction regions. There are two definitions of the pinning potential: maximum conduction band potential variation ($\Delta \varphi _{M}$) and maximum electron quasi-fermi level potential variation ($\Delta $ FP $_{M}$). The output of the previous pinning potential models is only an approximation of $\Delta \varphi _{M}$. In this paper, a comprehensive model is proposed in which both aforementioned definitions of pinning potential can be achieved analytically. The proposed model is a system of equations relating PPD’s main characteristics such as $\Delta \varphi _{M}$ and equilibrium full-well capacity to other main PPD parameters such as PPD spatial dimensions, impurity dopant concentrations, maximum inner region potential, and remnant carrier population at $\Delta \varphi _{M}$. The proposed model is verified by two previously reported experiment-based data. [ABSTRACT FROM AUTHOR]

Stacks of 2-D materials, known as van der Waals (vdW) heterostructures, have gained vast attention due to their interesting electrical and optoelectronic properties. This paper presents an intuitive circuit model for the out-of-plane electrostatics of a vdW heterostructure composed of an arbitrary number of layers of 2-D semiconductors, graphene, or metal. We explain the mapping between the out-of-plane energy band diagram and the elements of the equivalent circuit. Although the direct solution of the circuit model for an n-layer structure is not possible due to the variable, nonlinear quantum capacitance of each layer, this paper uses the intuition gained from the energy band picture to provide an efficient solution in terms of a single variable. Our method employs Fermi–Dirac statistics while properly modeling the finite density of states (DOS) of 2-D semiconductors and graphene. The approach circumvents difficulties that arise in commercial TCAD tools, such as the proper handling of the 2-D DOS and the simulation boundary conditions when the structure terminates with a nonmetallic material. Based on this methodology, we have developed 2dmatstacks, an open-source tool freely available on nanohub.org. Overall, this paper equips researchers to analyze, understand, and predict experimental results in complicated vdW stacks. [ABSTRACT FROM AUTHOR]

This paper demonstrates a high-performance black phosphorus nanoribbons field-effect transistor (BPNR-FET) and systematically investigates methods for enhancing its anisotropic carrier transport. The BPNR-FET shows a strong dependence on crystal orientation in which the best mobility performance is achieved in armchair-oriented nanoribbons. A downscaling of nanoribbon width is shown to improve the short-channel effect owing to a better electrostatic gate control. Furthermore, hydrogenation is employed to effectively passivate the dangling bonds and heal the nanoribbon edge defects, leading to nearly hysteresis-free transfer properties. By virtue of bandgap and contact-metal workfunction engineering, n-type BPNR-FET is successfully demonstrated, which enables complementary inverter circuits to be simultaneously realized. This paper unravels the superior performance underscores a conceptually new BPNR-FET, paving the way toward the development of non-planar devices and integrated circuits based on 2-D materials platform. [ABSTRACT FROM AUTHOR]

Part II of this paper discusses the transient characteristics of the electrically driven insulator–metal transition (E-IMT) material-based device. To model the full transient characteristics, we modify the electrothermal model developed in Part I to capture extrinsic capacitance and 2-D heat transport effects. In order to test the model against the experiment, we fabricated and tested scaled E-IMT devices with a necked-down design to minimize nonhomogeneity. We show excellent agreement of the predictions of the model with the experimental data, and we find that the IMT device goes through three stages before a steady state is established. These three stages are identified as the times required for the incubation of the IMT transition, positive feedback, and width expansion of the IMT zone within the device. The impact of capacitance and 2-D heat transport is discussed. Furthermore, we show an inverse relation arises between the incubation time and the applied voltage. This paper satisfactorily explains the turn-on transient in a nanoscale E-IMT device within the framework of our electrothermal (Joule heating) model. [ABSTRACT FROM AUTHOR]

This paper presents a new method for modeling the nonideal conductance response (CR) of synaptic devices. Unlike previous studies, which utilize physical device properties for modeling, this paper only uses the measured CR data. This allows the proposed modeling method to be easily applied to various types of synaptic devices without considering the unique physical properties of each device. An efficient piecewise linear approximation method which offers a tradeoff between computational complexity and simulation accuracy of neural networks is also presented to generate a linear device model out of nonlinear CR data. In addition, model parameters, which reflect the nonideal characteristics of the CR such as abrupt and asymmetric conductance changes, conductance variation, and limited conductance dynamic range, are introduced to evaluate the network performances in the presence of the nonidealities. By adjusting the model parameters, the desired CR satisfying the network performance requirements can be derived for device development. A three-layer neural network employing the device model has been designed and trained for the MNIST data set in order to demonstrate the application of the model to system-level simulations and verify the effectiveness of the modeling method. [ABSTRACT FROM AUTHOR]

This paper proposes a semianalytical model to estimate short-channel effects for independent gate operation in double-gate (DG) junctionless (JL) MOSFET incorporating gate-to-source/drain underlap, through the solution of Poisson’s equations in the subthreshold regime. The model also accounts for the asymmetry in device operation through variation in gate oxide thicknesses, gate work functions, and underlap lengths. Subthreshold drain current, threshold voltage, and subthreshold swing, evaluated from the channel potential, show reasonable agreement with simulation data. Results suggest the use of negative back gate bias and longer underlap length to reduce off-current. This paper highlights the role of doping, underlap length, and back gate bias in tuning the threshold voltage. This model serves as a generic formulation (within limits) with different asymmetries to estimate, design, and optimize self-aligned DG JL transistors for subthreshold logic applications. [ABSTRACT FROM AUTHOR]

Most thin-film transistor (TFT) gate drivers integrated on the display panel use the carry signals between the stages. In our previous works, we found that these carry-type gate drivers are subject to the reliability problem in a flexible display, since the errors of the stressed stages are accumulated through the carry signals. This problem possibly leads to the failure of image refresh of the display device. Therefore, the carry-free gate driver can resolve the error accumulation problem since it does not use the carry signals and instead, each unit stage operates independently. In this paper, we propose an advanced carry-free gate driver circuit to remove the drawbacks of the previous version, while keeping the advantages. More importantly, this paper is the first report to experimentally show that the error accumulation phenomenon of the carry-type gate driver and the problem is removed in the carry-free gate driver. The proposed carry-free gate driver and the carry-type gate driver are fabricated with amorphous indium-gallium-zinc-oxide TFTs on a flexible substrate for comparison purpose. The proposed gate driver shows a very high reliability since no voltage fluctuation occurs at the outputs after 10 000 cycles bending test with 2-mm bending radius. [ABSTRACT FROM AUTHOR]

This paper presents characterization and modeling results exploring the temperature dependence of the electrical characteristics of 3-D NAND Flash strings. Experimental data over a wide temperature range are used to calibrate a Technology Computer-Aided Design model for current transport through the polysilicon channel of the strings, which is then used to investigate the role of grain boundaries on string conduction. Results reveal that the variability in the grain configuration in the strings introduces a nonnegligible statistical spread in the temperature dependence of the threshold voltage (${V}_{T}$) of the memory cells, which acts as a broadening contribution to the array ${V}_{T}$ distribution when temperature is changed. The experimental and modeling activities will be extended in Part II of this paper to explore the temperature dependence of the ${V}_{T}$ instability caused by random telegraph noise. [ABSTRACT FROM AUTHOR]

A systematic analytical investigation of the charge distribution and gate control of the normally-off GaN double-channel MOS-HEMT (DC-MOS-HEMT) is presented in this paper. Compared to conventional GaN MOS-HEMT, the DC-MOS-HEMT features a thin AlN insertion layer (AlN-ISL) below the original two dimensional electron gas (2DEG) channel, thus forming a second channel at the interface between AlN-ISL and the underlying GaN. This paper reveals the impact of the AlN-ISL on the 2DEG distribution and the gate control of the channels. The sensitivity of ${V}_{\text {th}}$ against the recess depth is also analytically studied and is found to be nearly independent of the recess depth as long as the recess is terminated in the upper channel layer. The analytical results are well supported by numerical device simulations, and the physical mechanisms behind these findings are explained along with the analytical investigations. [ABSTRACT FROM AUTHOR]

This paper revisits the physics of current filamentation in grounded-gate NMOS (ggNMOS) devices and presents new physical insights which were not addressed in earlier works. A clear distinction between electrical and thermal instabilities is presented. Moreover, filament dynamics under electrical and thermal instability in both silicided and silicide blocked devices is discussed while highlighting observations which contradict with established theory of current ballasting. Interplay between electrical and thermal instabilities and its dependence on the presence or absence of silicide blocking is explored further. Filament spreading in ggNMOS devices and it is dependence on silicide blocking is discussed. Finally, while using the developed physical insights, missing correlation between TLP and HBM extracted failure current of silicided ggNMOS device is explained. [ABSTRACT FROM AUTHOR]

In this paper, we report on the influence of surface (donor and acceptor) states and interface charges on the formation of 2-D electron gas (2DEG) in MgZnO/ZnO heterostructure grown by sputtering. Donor and acceptor states alone cannot yield an order of magnitude higher value of 2DEG as observed by sputtering growth as compared to epitaxial techniques. While surface donor states are reported to govern the formation of 2DEG in epitaxially grown heterostructures, our simulations suggest a non-negligible contribution of surface acceptor states in the 2DEG density. In addition, the existence of interface charges due to high defect density along with appropriate values of donor and acceptor states is essential to accurately predict an order of magnitude higher 2DEG density grown by sputtering. This paper analyzes the distinct roles of donor and acceptor states along with interface charges in 2DEG formation and achieved values. [ABSTRACT FROM AUTHOR]

This paper presents an extensive investigation of the impact of the resistivity of the silicon substrate on the vertical leakage and charge trapping in 200 V GaN-on-Si enhancement-mode high-electron mobility transistors. Three wafers having different substrate resistivities were submitted to combined DC characterization, step-stress experiments, and electroluminescence (EL) analysis. The results described within this paper demonstrate that: 1) the use of a highly resistive silicon substrate can increase the vertical breakdown voltage of the transistors, due to the fact that the voltage drop on the GaN buffer is mitigated by the partial depletion of the substrate (this latter causes a plateau region in the drain to substrate I–V characteristic) and 2) highly resistive substrate results in stronger trapping effects, due to the capacitance of the depleted substrate and the resulting backgating effects. The results described within this paper indicate that the choice of the resistivity of the substrate is the result of a tradeoff between high breakdown voltage (that could be in principle achieved through a highly resistive substrate) and the minimization of trapping processes (which can be hardly obtained with a resistive substrate). [ABSTRACT FROM AUTHOR]

In this paper, we present a comprehensive study of multisection, velocity-tapered slow wave structures (SWSs) for highly efficient backward-wave oscillators (BWOs). The SWS velocity variation profiles are characterized by mathematical functions. Using particle-in-cell (PIC) simulations, the efficiencies of these SWSs are obtained along with their oscillation frequency response to variations in beam voltage. This paper is aimed at determining the optimum SWS profiles for high-efficiency BWO operation along with the corresponding tunability. The profile with the highest possible efficiency is fabricated and cold tested to experimentally determine and validate the underlying efficiency enhancement mechanisms. This resulting cold test experiment demonstrates higher order dispersion in the form of multiple secondary inflection points. PIC simulations using this SWS design predict an output power of 8.25 MW at 2.62 GHz corresponding to a peak power conversion efficiency of 70%. [ABSTRACT FROM AUTHOR]

The weight percentage of scandia nanoparticles in scandate cathodes was varied and found to have a critical impact on emission performance and predictability. The conventional concentration of 4–5 wt% scandia was found to be too high and is discussed. Large numbers of cathodes were characterized via Scanning Electron Microscopy/Energy Dispersive X-ray Spectroscopy cross sections, then emission tested in close-spaced diodes. The balance or ratio of barium–calcium–aluminate to scandium oxide was found to be the most important factor in predicting a cathode’s operating temperature. Excessive scandia inhibited the flow of molten impregnant into matrix pores. Furthermore, excessive scandia was found to lower matrix mechanical strength. This work also revealed the importance of lowering the oxygen content in tungsten particles prior to sintering. Large numbers of dry-hydrogen-fired powders were compared to wet-hydrogen-fired ones and were found to have much higher emission performance. Four different powder types were studied, including those from a novel two-stage liquid–liquid (L–L) precipitation technique, ones from single L–L precipitation, and ones from the liquid–solid (L–S) precipitation technique. This paper also reports life test results on selected cathodes. [ABSTRACT FROM AUTHOR]

The need for information transmission at ever increasing data rates is moving satellites to the millimeter-wave (MMW) bands. The efficient transmission of information requires linear systems. For satellites transmission linear, high-power amplifiers (HPAs) are essential in both orbit and on the ground. This paper describes linearizers that have been developed for the use with TWTAs at Q (43.5–45.5 GHz) and the new V (47–52 GHz) satellite bands. This paper will also discuss linearizer work for even higher bands that will be needed in the near future. Today’s TWTA linearizers can provide all the frontend functions needed by an HPA including upconversion, gain, commandable attenuation, commandable predistortion, and the RF power for direct drive. The use of linearization at MMW is discussed and measured characteristics of the linearizers such as power transfer and carrier to intermodulation (IM) ratio (C/I) shared. Linearized MMW TWTAs are shown to achieve an AM/PM of <2°/dB, and at 3-dB output power backoff with a 16QAM signal, an adjacent channel power ratio of >30 dB with an error vector magnitude of <2%. [ABSTRACT FROM AUTHOR]